2D Phase-Change Ternary CMOS for Low-Power Logic Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CMOS devices face challenges in reducing power consumption, especially in large-scale information processing using binary elements, and struggle with process dispersion due to doping, limiting their robustness and integration density.
Innovation Solution
A ternary CMOS device is developed using a two-dimensional material layer with a phase change material, allowing n-type and p-type MOSFET regions to operate without separate doping, enabling ternary operations and supporting a wide range of operating speeds by controlling the thickness of the two-dimensional phase change material layer, which acts as a resistor to limit current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If binary elements are used in CMOS devices, then the device structure is simple and manufacturing is easy, but power consumption cannot be reduced sufficiently in large-scale information processing
Solution Approach 1:
The patent changes the fundamental operational parameter of CMOS devices from binary (0, 1) to ternary (0, 1, 2) logic operations. By introducing a two-dimensional material layer with phase change properties that can exist in three distinct conductivity states, the device achieves ternary logic operations, thereby reducing power consumption while maintaining computational capability through increased operational versatility.
Solution Approach 2:
The patent employs a composite structure combining conventional CMOS components with a two-dimensional material layer (such as transition metal dichalcogenides). This composite material system integrates the electrical control capabilities of CMOS with the phase-change properties of 2D materials, enabling ternary operations and solving the power consumption problem while preserving device adaptability.
2Reliability
If separate doping is used to create n-type and p-type regions, then device functionality is achieved, but process dispersion occurs reducing robustness and stability
Solution Approach 1:
The patent extracts and eliminates the separate doping processes from the manufacturing workflow. Instead of using conventional doping methods to create n-type and p-type regions, the invention relies on the inherent properties of two-dimensional materials that can be controlled through voltage changes and phase transitions, thereby removing the source of process dispersion while maintaining device functionality.
Solution Approach 2:
The two-dimensional material layer inherently provides the functionality that would otherwise require separate doping processes. The material's ability to change conductivity states through voltage control and phase transitions enables it to self-regulate its electrical properties without external doping, improving reliability by eliminating process dispersion while simplifying manufacturing steps.
3Productivity
If integration density is increased, then device performance improves, but power consumption and process dispersion problems worsen
Solution Approach 1:
The patent utilizes parameter changes in the two-dimensional material layer, specifically controlling its thickness and phase state, to enable ternary logic operations. This allows higher integration density because ternary devices can perform more computational work per unit area compared to binary devices, while the phase-change mechanism enables low-power operation through non-volatile state retention and reduced switching energy requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ternary CMOS device achieves robust and stable operation across various power environments, from ultra-low power to high performance, with increased integration density and reduced power consumption by utilizing a two-dimensional phase change material that changes conductivity with voltage, thus simplifying circuit complexity and reducing power requirements.
Implementation Method 1
the two-dimensional material layer includes a two-dimensional phase change material layer formed of a two-dimensional phase change material
Implementation Method 2
the two-dimensional phase change material layer... acts as a resistor to limit current flow
Data Source
AI summary
Disclosed is a ternary CMOS device including a two-dimensional material layer formed of a two-dimensional material, an n-type MOSFET region stacked on a top of the two-dimensional material layer, and a p-type MOSFET region stacked on the top of the two-dimensional material layer, wherein the two-dimensional material layer includes a two-dimensional phase change material layer formed of a two-dimensional phase change material, an n-channel two-dimensional semiconductor material layer stacked on a bottom of the n-type MOSFET region and connected to one end of the two-dimensional phase change material layer, and a p-channel two-dimensional semiconductor material layer stacked on a bottom of the p-type MOSFET region and connected to the other end of the two-dimensional phase change material layer.