Ternary Inverter Threshold Layout for Lower VDD/2 Static Current
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Solution Overview
Problem
The implementation of ternary logic circuits faces challenges in reducing static current and power dissipation, particularly when the output voltage is at the half drain voltage VDD/2, due to incomplete turn-off of transistors with insufficient threshold voltage.
Innovation Solution
The use of transistors with different threshold voltages in the design of the ternary inverter, where P-MOS transistors with a second threshold voltage higher than the first threshold voltage are used to reduce current flow when the output is at VDD/2.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If transistors with standard threshold voltage are used in ternary logic circuits, then the circuit can operate with standard voltage levels, but static current increases and power dissipation increases when output is at VDD/2
Solution Approach 1:
The patent applies local quality by assigning different threshold voltage characteristics to different transistors within the ternary logic circuit. Specifically, pull-up transistors are designed with higher threshold voltages than pull-down transistors, creating localized electrical property differences that optimize circuit performance. This selective differentiation of transistor characteristics reduces static current flow while maintaining reliable operation at various voltage levels including VDD/2
Solution Approach 2:
The patent implements parameter changes by modifying the threshold voltage parameter of transistors based on their functional role in the circuit. By adjusting the threshold voltage of pull-up transistors to be higher than that of pull-down transistors, the circuit achieves reduced power dissipation while maintaining operational reliability. This parameter optimization is particularly effective when the output is at the intermediate voltage level VDD/2
2Loss of energy
If transistors with higher threshold voltage are used to reduce current flow, then power dissipation decreases, but the transistor turn-off becomes incomplete at VDD/2 output
Solution Approach 1:
The patent resolves the switch state stability issue by applying local quality differently to pull-up and pull-down transistors. Pull-down transistors maintain standard or lower threshold voltages to ensure complete turn-off and stable low state, while pull-up transistors use higher threshold voltages to minimize current flow. This asymmetric local optimization allows the circuit to achieve both reduced power dissipation and maintained switch state stability
Solution Approach 2:
The patent uses parameter changes by selectively modifying threshold voltage based on transistor function. Pull-down transistors are designed with threshold voltages optimized for complete turn-off to maintain stable switch states, while pull-up transistors use higher threshold voltages to reduce current flow. This differentiated parameter assignment resolves the contradiction between current reduction and switch state stability
3Area of stationary object
If multi-valued logic system is implemented to reduce silicon area and power consumption, then routing wire area and power consumption decrease, but the complexity of logic gate implementation increases
Solution Approach 1:
The patent applies segmentation by dividing the ternary logic gate into distinct functional components with specific transistor configurations. The circuit is segmented into pull-up networks and pull-down networks with clearly defined transistor roles, making the implementation more manageable despite the inherent complexity of multi-valued logic. This structured segmentation helps in systematically handling the increased design complexity
Solution Approach 2:
The patent reduces implementation complexity by applying local quality principles to create standardized transistor configurations within the multi-valued logic gates. By using consistent threshold voltage assignments for similar transistor roles across different logic gates, the patent creates reusable design patterns that simplify the overall implementation complexity while maintaining the area and power benefits of multi-valued logic
Data Source
AI summary
Disclosed is an inverter which includes a first P-MOS transistor connected between a node receiving a drain voltage and a first path node and operated based on an input voltage, a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage and operated based on the drain voltage, a second P-MOS transistor connected between the output terminal and a second path node and operated based on a ground voltage, a second N-MOS transistor connected between the second path node and a node receiving the ground voltage and operated based on the input voltage, a third P-MOS transistor connected between the first path node and the second path node and operated based on the input voltage, and a third N-MOS transistor connected between the first path node and the second path node and operated based on the input voltage.