Clock Embedded Differential Data Receiving System for Ternary Lines
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Solution Overview
Problem
There is no effective differential data receiving system for efficiently receiving differential data transferred via Ternary Lines Differential Signaling (TDLS), which increases the number of transfer lines and complicates layout area usage.
Innovation Solution
A clock embedded differential data receiving system that monitors voltage levels of ternary lines to generate clock and pre-data signals, using comparators to determine logic states and a timing controller to delay the clock signal, allowing for efficient decoding and sampling of output data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential signaling is used to transfer data, then noise immunity and speed are improved, but the number of transfer lines increases and layout area is consumed
Solution Approach 1:
The patent merges multiple differential signal lines into a single ternary line that can represent three different logic states (0, 1, 2) through different voltage level combinations. This allows 3 bits of data to be transmitted using what would traditionally require more differential signal lines, thereby reducing the layout area while maintaining the noise immunity benefits of differential signaling.
Solution Approach 2:
The patent changes the signaling parameter from binary (two voltage levels) to ternary (three voltage levels) differential signaling. By using three distinct voltage level combinations instead of two, the system can encode more information per line, reducing the total number of lines needed and thus the layout area.
2Productivity
If ternary lines differential signaling is used to increase data transfer capacity, then data bits per transfer line are increased, but no efficient differential data receiving system exists
Solution Approach 1:
The receiving system is segmented into functional modules: a monitoring portion that detects voltage levels, a data generating portion that creates clock and pre-data signals, and a timing controller that manages sampling. This modular approach makes the complex task of receiving ternary differential data more manageable and implementable.
Solution Approach 2:
The system performs preliminary actions by generating clock signals and pre-data signals before the actual data sampling occurs. The timing controller prepares the sampling control signal in advance, ensuring that data is sampled at the optimal moment. This preliminary preparation simplifies the overall receiving process.
3Reliability
If voltage levels of ternary lines are monitored to generate clock signals, then data reception is enabled, but timing control and sampling precision become critical
Solution Approach 1:
The timing controller uses feedback from the voltage level monitoring to generate accurate timing control signals. By continuously monitoring the voltage levels and using this information to adjust the sampling timing, the system maintains high precision in data reception without requiring extremely tight manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the reception of 3-bit data using the clock signal, improving data transfer efficiency and reducing the complexity of layout area usage by effectively decoding ternary line signals.
Implementation Method 1
a monitoring portion which monitors voltage levels of the first, second and third transfer signals, and generates a clock signal... wherein the clock signal includes a logic state according to a comparison of the voltage levels between the first transfer signal and the second transfer signal
Implementation Method 2
a timing controller which delays the transition time point of the clock signal with a delay phase and generates the sampling control signal
Implementation Method 3
a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group which decodes the first pre-data and the second pre-data
Data Source
AI summary
A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.