Ternary Logic Circuit Using CNTFETs to Cut Power Density
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Solution Overview
Problem
The performance of computing systems is hindered by increasing power density in fine semiconductor processes, which existing technologies fail to adequately address through binary logic, necessitating a more efficient logic method.
Innovation Solution
A ternary logic circuit device is designed using transistors, specifically incorporating single-walled carbon nanotube field-effect transistors (CNTFETs) to implement ternary logic gates that operate with three voltage levels, reducing circuit complexity and power consumption by utilizing drain, half drain, and ground voltages to represent logical values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If binary logic is used in fine semiconductor processes, then computing performance can be maintained with existing technology, but power density increases exponentially
Solution Approach 1:
The patent changes the fundamental parameter of logic states from binary (2 states) to ternary (3 states). By using three distinct voltage levels (drain voltage, half drain voltage, and ground voltage) to represent three logic states, the system achieves higher computational density and efficiency while reducing power consumption compared to traditional binary logic in fine semiconductor processes.
2Device complexity
If ternary logic gates are implemented using transistors, then circuit complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the transistor gate control into multiple distinct voltage levels (drain, half drain, ground) that can be independently generated and controlled. This segmentation allows the complex ternary logic operations to be broken down into manageable voltage control stages, reducing the overall circuit complexity while maintaining manufacturability through standardized transistor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ternary logic circuit device effectively reduces power consumption and circuit complexity, improving computing performance by utilizing a three-state logic system that efficiently manages input signals and outputs corresponding voltage levels.
Implementation Method 1
a channel between a source and a drain, the channel comprising a single-walled carbon nanotube
Data Source
AI summary
A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.