Ternary Memory Error Correction via Binary Auxiliary Read Values
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Solution Overview
Problem
Conventional error correction and detection techniques are inadequate for memories with memory cells that can take on more than two states, particularly ternary memory cells, which require improved methods for error correction.
Innovation Solution
A circuitry system that includes a memory with ternary memory cells, a subcircuit to generate output values based on binary inputs, an encoder to generate binary check bits, and a corrector to perform error correction, ensuring that the binary auxiliary read values and check bits form error-free codewords, stored in memory cells capable of multiple states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional error correction techniques are used for ternary memory cells, then the memory can store more data per cell, but the error correction capability becomes inadequate
Solution Approach 1:
The patent segments the error correction process into multiple specialized subcircuits: a first subcircuit for generating output values from binary inputs, a second subcircuit for reading state values and determining binary auxiliary read values, and a corrector subcircuit for generating error correction bits. This segmentation allows each subcircuit to be optimized for its specific function, enabling reliable error correction in ternary memory systems while maintaining high storage capacity.
Solution Approach 2:
The patent introduces binary auxiliary read values as an intermediary between the ternary state values read from memory and the error correction process. These auxiliary values serve as a bridge that translates multi-state memory contents into a binary format that can be processed by conventional error correction codes, thereby enabling error correction capability in ternary memory systems without sacrificing storage density.
2Quantity of substance
If ternary memory cells are used instead of binary memory cells, then storage density increases, but the complexity of error correction circuitry increases
Solution Approach 1:
The patent employs error correcting codes that operate on binary auxiliary read values derived from ternary state values. This approach allows the use of well-established binary error correction techniques for ternary memory, reducing circuit complexity. The encoder generates check bits that work with both binary and ternary representations, creating a universal error correction mechanism that handles ternary memory errors without requiring entirely new complex algorithms.
Solution Approach 2:
The patent replaces direct ternary error correction mechanisms with a binary-based error correction system. Instead of developing complex ternary-specific error correction logic, the invention uses binary auxiliary values and binary error correction codes to handle errors in ternary memory cells. This substitution leverages成熟binary error correction hardware, reducing overall circuit complexity while maintaining effective error correction for high-density ternary storage.
3Quantity of substance
If multi-state memory cells are implemented, then memory capacity per cell increases, but the difficulty of detecting and measuring error-free states increases
Solution Approach 1:
The patent uses binary auxiliary read values as an intermediary to simplify the detection of error-free states in ternary memory cells. By converting ternary state values into binary auxiliary values through the second subcircuit, the system can apply binary error detection and correction logic, making it easier to identify and correct errors while maintaining the high storage capacity of multi-state memory cells.
Solution Approach 2:
The patent implements feedback through error correction bits generated by the corrector subcircuit. These check bits provide feedback information about the validity of stored data, allowing the system to detect and correct errors in ternary memory cells. The feedback mechanism works with binary auxiliary values, simplifying the detection process while maintaining the ability to verify error-free states in high-capacity multi-state memory.
Data Source
AI summary
A circuitry is provided that includes a memory including a plurality of memory cells, wherein at least one of the plurality of memory cells of the memory is configured to take on one of at least three different states. The circuitry also includes a first subcircuit BT configured to generate a plurality of ternary output values based on a sequence of binary values, a second subcircuit LH configured to transform one or more ternary state values into binary auxiliary read values based on the one or more state values, and an encoder configured to generate one or more binary check bits, wherein the encoder is configured to store each of the generated one or more check bits in a different memory cell.