Ternary Memory Cell Logic-In-Memory Architecture
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Solution Overview
Problem
Existing memory devices lack the capability to efficiently perform logic operations on ternary logic values, which limits their information processing capacity and requires external logic devices for processing ternary logic operations.
Innovation Solution
A memory device with a cell array of ternary memory cells, each including a logic operation circuit with P-channel and N-channel transistors that can perform constant current operations, allowing for logic operations on ternary values and reducing the need for external logic devices by integrating logic operations within the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory device uses traditional binary logic circuits with ground voltage and positive supply voltage, then the device structure is simple, but the information processing capacity is limited
Solution Approach 1:
The patent merges memory storage function with logic operation function into a single ternary memory cell structure. The cross-coupled inverters that form the memory cell also perform ternary logic operations (AND, OR, NAND, NOR) by utilizing the three stable voltage states (0V, VDD/2, VDD), eliminating the need for separate logic circuits and thereby increasing information processing capacity while managing device complexity
Solution Approach 2:
The patent changes the voltage parameter system from binary (two voltage levels) to ternary (three voltage levels: 0V, VDD/2, VDD). This parameter change enables the memory cell to store and process three logic states (0, 1, 2) simultaneously, tripling the information density and processing capacity per cell compared to traditional binary systems
2Productivity
If logic operations are performed outside the memory device, then the memory device structure remains simple, but the logic operation time increases
Solution Approach 1:
The patent combines logic operation circuits directly within the memory device structure, specifically integrating AND, OR, NAND, and NOR logic gates into the ternary memory cell architecture. This integration allows logic operations to be performed in-situ during memory access operations, dramatically reducing logic operation time and improving productivity
Solution Approach 2:
The ternary memory cell structure is designed to perform multiple functions: data storage in three states, ternary logic operations (AND, OR, NAND, NOR), and data output. This multi-functionality eliminates the need for external logic devices and enables the memory device to process information at memory speed, significantly improving logic operation speed
3Device complexity
If external logic devices are used for ternary logic operations, then the memory device structure is simple, but the overall system complexity increases
Solution Approach 1:
The patent merges the logic operation capability directly into the memory device by implementing ternary logic gates within the memory cell structure. The cross-coupled inverter configuration inherently supports multiple logic operations through selective activation, eliminating external logic devices and reducing overall system complexity while maintaining full ternary logic operation capability
Solution Approach 2:
The patent extracts the logic operation function from external separate devices and integrates it directly into the memory cell structure. By embedding AND, OR, NAND, and NOR gates within the memory device, the system eliminates external logic components, reducing overall system complexity while preserving complete ternary logic operation capability
Data Source
AI summary
According to an embodiment of the present disclosure, a memory device for a logic-in-memory may include a cell array including a plurality of ternary memory cells, a row decoder configured to select at least one ternary memory cell from among the plurality of ternary memory cells, and a page buffer configured to provide a first value to the at least one ternary memory cell and latch a third value obtained by performing a logic operation on the first value and a second value stored in the at least one ternary memory cell and/or the second value. The at least one ternary memory cell may include: a first inverter and a second inverter, cross-coupled in a first node corresponding to the second value and a second node corresponding to an inverted value of the second value, and including a pull-up device and a pull-down device, wherein the pull-up device and the pull-down device are configured to have a constant current pass therethrough upon turn-off; and a logic operation circuit including a P-channel transistor and an N-channel transistor and configured to output the third value, wherein the P-channel transistor and the N-channel transistor are configured to have the constant current pass therethrough upon turn-off.