Ternary MOSFET Logic Circuit Using PHN to Eliminate Static Current
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Solution Overview
Problem
Conventional ternary circuit designs face significant static power consumption due to short-circuit currents when expressing the intermediate state '0', limiting their efficiency and scalability.
Innovation Solution
A method for designing ternary logic circuits using depletion-mode MOSFETs with multiple threshold voltages, employing a pull-half network (PHN) composed of connected DEP-FETs, and configuring pull-up and pull-down networks with MOSFETs having different threshold voltages to minimize static current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ternary circuit designs use voltage distribution with passive elements or voltage drop with active elements to express intermediate state '0', then the ternary logic functionality is achieved, but very large static power consumption occurs due to short-circuit current between GND and VDD
Solution Approach 1:
The patent changes the operational parameters of MOSFETs by using depletion-mode devices with multiple threshold voltages. By configuring PHN with DEP-FETs and PUN/PDN with multi-VTH MOSFETs, the circuit achieves ternary logic states without creating direct conductive paths between VDD and GND, thereby eliminating short-circuit current and reducing static power consumption while maintaining reliable ternary logic functionality.
2Productivity
If device miniaturization continues in binary computing systems, then integration technology improves, but the difficulty of technology rapidly increases and development reaches its limit at several nm-scale
Solution Approach 1:
The patent employs depletion-mode MOSFETs with multiple threshold voltages that can operate in different modes (depletion and enhancement) and provide multiple logic states. This multi-functionality allows the same device structure to implement ternary logic operations, reducing the need for additional specialized components and simplifying the overall circuit architecture compared to binary systems at equivalent computational density.
3Productivity
If ternary computing system is implemented to reduce computing numbers and storage space, then high-density and high-performance are achieved, but very large static power consumption occurs in conventional designs
Solution Approach 1:
The patent applies different characteristics to different parts of the circuit: PHN uses DEP-FETs for low-power operation in the intermediate state, while PUN and PDN use MOSFETs with different threshold voltages optimized for their specific functions. This local optimization ensures that each part of the circuit contributes to low static power consumption while maintaining the overall high-density and high-performance ternary computing capability.
Data Source
AI summary
Provided is a method of designing a ternary logic circuit using MOSFETs having a depletion-mode and multiple threshold voltages, and the method includes configuring a pull-half network (PHN) by connecting two or more DEP-FETs, configuring one or more of a PUN and a PDN with one or more MOSFETs having different threshold voltages, and connecting the PHN to one or more of the PUN and the PDN. Accordingly, it is possible to design a ternary logic circuit that enables low-power operation because there is no static current consumption, which is a chronic problem of the ternary circuits, in all logic states including an intermediate state ‘0.’