Ternary Weight Cell Circuit for Low-Power Logic-in-Memory
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Solution Overview
Problem
Existing memory devices face challenges in maximizing computational efficiency with low power consumption and area efficiency due to the use of binary CMOS-based memory cells, which result in increased power consumption and area requirements when transitioning to ternary information storage.
Innovation Solution
A T-CMOS-based ternary weight cell circuit design is implemented, utilizing a ternary memory cell with three transistors to store ternary data and control current flow based on weight and activation signals, reducing the number of transistors and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a binary CMOS-based memory cell is used to store ternary information, then area efficiency is improved, but power consumption increases and energy efficiency decreases
Solution Approach 1:
The patent changes the fundamental parameter of the memory cell from binary (0, 1) to ternary (0, 1, 2) by introducing a new transistor configuration with three transistors. This parameter change allows storing more information per cell without increasing area, while the ternary logic circuit reduces unnecessary computation operations, thereby improving energy efficiency and reducing power consumption.
Solution Approach 2:
The memory cell is segmented into functional components: a ternary memory cell for storing ternary data (0, 1, 2) and a weight cell with three transistors for controlling current flow based on weight signals. This segmentation allows independent optimization of storage and computation functions, achieving high area efficiency while reducing power consumption through selective current control.
2Reliability
If two memory cells are used to store ternary information, then ternary storage capability is achieved, but area increases by double or more
Solution Approach 1:
The patent merges the storage and computation functions into a single integrated ternary memory cell structure. By combining the ternary memory cell with a weight cell that has three transistors, the system achieves ternary storage capability within a compact area, avoiding the need for separate memory cells and reducing overall area consumption.
Solution Approach 2:
The ternary memory cell structure serves multiple functions: it stores ternary data (0, 1, 2), controls current flow through the weight cell transistors, and enables logic-in-memory operations. This multi-functionality eliminates the need for additional dedicated memory cells, achieving ternary storage capability without doubling the area.
3Area of stationary object
If CMOS density is improved to increase storage capacity, then area efficiency increases, but standby power consumption increases due to increased leakage current
Solution Approach 1:
The weight cell uses periodic control signals (activation signals and weight signals) to enable current flow only when computation is needed. During standby periods, the transistors remain off, blocking leakage current and reducing standby power consumption while maintaining high area efficiency through the compact ternary structure.
Solution Approach 2:
The patent discards the continuous current flow approach in favor of selective current control. The weight cell transistors are activated only when weight signals and activation signals are present, discarding unnecessary current flow during standby and recovering energy by blocking leakage current, thereby reducing standby power consumption while maintaining area efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves high area efficiency and low power consumption by storing information at a low current, enhancing energy efficiency and reducing standby power consumption.
Implementation Method 1
a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell
Data Source
AI summary
Provided is a memory device for a logic-in-memory. The memory cell includes: a ternary memory cell for storing ternary data: and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line.