Ternlog Packed Instruction for Boolean Function Indexing
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Solution Overview
Problem
The performance of SHA-2 hash functions, such as SHA-256, is low on general-purpose processor cores due to the large number of bitwise logical operations that consume instructions and add to the critical path of the round function, which is also a limitation in other secure hashing algorithms like SHA-1 and MD5, as these operations often require splitting into operations on at most two operands.
Innovation Solution
A new instruction format is introduced to efficiently execute Boolean functions with three operands by using a truth-table immediate value to compute any Boolean function, allowing for the execution of bit-wise logical operations in a single processor cycle, specifically through the Ternlog_packed instruction which packs three source operands and an immediate value to perform operations like Majority, Choose, and Parity functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional two-operand bitwise logical operations are used to implement three-operand Boolean functions, then the operations can be executed on general-purpose processor cores, but the number of instructions increases and the critical path of the round function lengthens, reducing performance
Solution Approach 1:
The patent merges multiple two-operand operations into a single three-operand Boolean instruction. The execution unit is modified to accept three source operands (a, b, c) and an immediate value, performing the Boolean function f(a, b, c, imm) in one operation instead of requiring multiple separate instructions. This combining of operations directly reduces the instruction count and shortens the critical path, resolving the performance limitation.
Solution Approach 2:
The patent extends the traditional two-operand instruction space by adding a third operand dimension. The execution unit now processes three source registers plus an immediate value, creating a four-dimensional input space (a, b, c, imm) that enables direct implementation of three-operand Boolean functions. This dimensional expansion allows the processor to execute cryptographic hash functions more efficiently without requiring multiple instructions.
2Adaptability or versatility
If three-operand Boolean functions are implemented by splitting into two-operand operations, then the operations can be executed on processors without three-operand instruction support, but the operation count increases and execution efficiency decreases
Solution Approach 1:
The execution unit is enhanced with self-service capabilities to natively support three-operand Boolean functions. Instead of relying on software decomposition into two-operand operations, the hardware itself is modified to directly accept and process three source operands and an immediate value. The execution unit performs the full three-operand Boolean function f(a, b, c, imm) in a single operation, eliminating the need for software workarounds and achieving both architectural adaptability and high execution efficiency.
3Reliability
If multiple instructions are used to perform bit-wise logical operations, then the operations can be completed on general-purpose processors, but the instruction throughput decreases and the round function execution time increases
Solution Approach 1:
The execution unit is pre-configured with the capability to handle three-operand Boolean functions natively. The hardware design anticipates the needs of cryptographic hash functions by incorporating dedicated logic that can process three source operands and an immediate value in a single cycle. This preliminary hardware preparation eliminates the need for multiple sequential instructions, directly reducing the execution time of round functions while maintaining execution correctness.
Data Source
AI summary
An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, in one embodiment, a processor comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.