Terraced Gate Oxide Structure for Lower MOSFET Gate-Drain Capacitance
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Solution Overview
Problem
High power devices, such as VDMOSFETs, suffer from high parasitic gate to drain capacitance (CGD) which affects switching speed and power consumption, and existing methods have not adequately addressed this issue without compromising device reliability and breakdown voltage.
Innovation Solution
A fabrication method is developed to form a terraced gate oxide structure with a thicker oxide layer thickness in the JFET region and a semi-sunken design, achieved through high temperature and room temperature ion implantation processes, followed by thermal oxidation, to reduce CGD and suppress electric field crowding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar gate oxide structure is used, then the device structure is simple and manufacturing is easy, but the parasitic gate to drain capacitance (CGD) is high which affects switching speed and power consumption
Solution Approach 1:
The gate oxide structure is segmented into multiple regions with different thicknesses: a first gate oxide region over the channel region and a second gate oxide region over the JFET region. This segmentation allows the oxide thickness to be optimized independently in each region, reducing CGD in the JFET region while maintaining proper gate control over the channel region.
Solution Approach 2:
Different oxide thicknesses are applied to different locations: the second gate oxide region has a greater thickness than the first gate oxide region. This local quality variation reduces the parasitic capacitance in the JFET region where high voltage stress occurs, while preserving the necessary electrical characteristics in the channel region.
2Reliability
If the gate oxide thickness is increased to reduce parasitic capacitance, then CGD is reduced, but the electric field crowding and enhancement effect at the gate electrode corners is generated
Solution Approach 1:
The gate oxide thickness is locally varied to address different electrical requirements: thicker oxide over the JFET region reduces CGD and associated electric field stress, while thinner oxide over the channel region maintains proper gate control and avoids excessive field concentration at the corners.
Solution Approach 2:
The solution transitions from a two-dimensional planar oxide structure to a three-dimensional terraced structure with varying thickness. This dimensional change allows the oxide to provide both capacitance reduction and field management functions simultaneously by creating a gradient in electrical properties across the device structure.
3Reliability
If a terraced gate oxide structure with thicker oxide in JFET region is formed, then parasitic capacitance is reduced, but the manufacturing process becomes more complex requiring multiple ion implantation steps
Solution Approach 1:
An amorphous layer is formed preliminarily over the JFET region through ion implantation before the thermal oxidation step. This preliminary action creates a localized region that will oxidize at a different rate, enabling the formation of the terraced structure in a single oxidation process rather than requiring multiple sequential oxidation steps.
Solution Approach 2:
The fabrication process utilizes parameter changes in the thermal oxidation step by controlling temperature, time, and atmosphere to achieve differential oxidation rates between the amorphous layer region and the crystalline silicon region. This allows the complex terraced structure to be formed through controlled parameter variation rather than complex mechanical or chemical etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic gate to drain capacitance, enhances device reliability, and maintains breakdown voltage by forming a terraced gate oxide structure with increased thickness and reduced corner curvature.
Implementation Method 1
a thermal oxidation process is successively adopted so as to oxidize the amorphous layer, and a terraced gate oxide is formed
Implementation Method 2
a first ion implantation process is performed through the first spacing, and a second ion implantation process is performed through the second spacing
Data Source
AI summary
A fabrication method for forming a terraced gate oxide and the formed terraced gate oxide structure are provided. Sidewall barrier layers are provided in a high power device after high-temperature JFET ion implementation process. A second ion implementation process is subsequently applied under room temperatures to form an amorphous layer at the JFET top surface. After removing hard masks and sidewall barrier layers, rest processes are carried out. As for growing the gate oxide, since oxidation rate of the amorphous layer is greatly higher than that of the channel region and of the JFET region, a terraced gate oxide structure can be fabricated. Meanwhile, a bottom of the terraced gate oxide structure is underneath the device surface. The present invention is thus advantageous of reducing both the parasitic gate to drain capacitance and corner curvature of the gate electrode, thereby reduce electric field enhancement effects and avoid reliability degradation.