Tessellating Surface Data Patches for Tile-Based Graphics Culling

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Solution Overview

Problem

Tile-based computer graphics rendering systems face increased data transfer, storage, and processing requirements due to the large number of tessellated primitives, which can significantly hinder rendering efficiency.

Innovation Solution

The method involves subdividing the rendering space into tiles, tessellating a patch of surface data to derive primitives, analyzing a portion of the patch to determine a bounding depth value for each tile, and rendering only non-hidden portions of the patch, thereby reducing processing and memory bandwidth by culling hidden primitives.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If tessellation is applied to add texture to surface data, then visual quality and detail are improved, but the amount of computation and processing required increases substantially

Engineering Contradiction:
Improvevisual qualityVSAvoidcomputation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing bounding depth value analysis on tessellated patches before they are fully processed and rendered. By evaluating the minimum and maximum depth values of tessellated primitives in advance and comparing them against the z-buffer, the system can determine whether a patch is visible or hidden before committing full processing resources, thus reducing computation complexity while maintaining visual quality

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the essential visibility determination function from the full rendering process by isolating the bounding depth value evaluation. Instead of processing all tessellated primitives through the complete rendering pipeline, the system extracts only the depth analysis component to perform early culling, separating the visibility test from the full geometric processing and reducing overall computation requirements

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If each tessellated primitive is processed individually for hidden surface removal, then rendering accuracy is improved, but data transfer and processing time increase

Engineering Contradiction:
Improverendering accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent merges multiple individual primitive processing operations into a single patch-level operation. By combining all tessellated primitives from a patch into a unified bounding depth value evaluation, the system performs one visibility test per patch rather than one test per primitive. This merging maintains rendering accuracy by still evaluating the actual tessellated geometry, while dramatically reducing processing time and data transfer requirements

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If all tessellated primitives are stored in memory, then complete geometric data is preserved, but memory bandwidth and storage requirements increase

Engineering Contradiction:
Improvedata completenessVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential geometric information needed for visibility determination - specifically the minimum and maximum depth values of tessellated primitives - and stores this extracted data in the z-buffer. Instead of storing complete geometric data for all tessellated primitives in memory, the system extracts and retains only the depth range information required for hidden surface removal, significantly reducing memory bandwidth and storage requirements while preserving sufficient data for accurate rendering decisions

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20230088494A1Tessellating patches of surface data in tile based computer graphics rendering
Publication Date: 2023.03.23 IMAGINATION TECH LTD
  • US20230088494A1 patent drawing
  • US20230088494A1 patent drawing
  • US20230088494A1 patent drawing

AI summary

A method and system for culling a patch of surface data from one or more tiles in a tile based computer graphics system. A rendering space is divided into a plurality of tiles and a patch of surface data read. Then, at least a portion of the patch is analysed to determine data representing a bounding depth value evaluated over at least one tile. This may comprise tessellating the patch of surface data to derive a plurality of tessellated primitives and analysing at least some of the tessellated primitives. For each tile within which the patch is located, the data representing the bounding depth value is then used to determine whether the patch is hidden in the tile, and at least a portion of the patch is rendered, if the patch is determined not to be hidden in at least one tile.