Test Access Mechanism for SoC Using Functional Fabric
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Solution Overview
Problem
The verification of System on a Chip (SoC) designs is challenging due to the need for flexible and predictive testing of communication between IP blocks and IP functionality, which is currently hindered by ad-hoc Test Access Mechanisms (TAMs) that increase area and wiring congestion, jeopardizing Time-To-Market and cost goals.
Innovation Solution
A standard, modular, scalable, and reusable Test Access Mechanism (TAM) is implemented using existing functional fabrics like Intel On-Chip Scalable Fabric (IOSF), comprising a Test Controller and Test Wrapper to deliver test stimulus and sample responses, reducing gate count and global routing, and enabling flexible and efficient testing without dedicated test infrastructure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ad-hoc Test Access Mechanisms (TAMs) are used for testing IP blocks in SoC, then testing flexibility is improved, but area and wiring congestion increase
Solution Approach 1:
The patent applies universality by making the functional fabric serve multiple purposes: it acts as both the operational interconnect for data transmission between IP blocks and as the test access mechanism for verification. The same fabric infrastructure is used for both normal SoC operation and testing, eliminating the need for separate dedicated test wiring and reducing overall area requirements.
Solution Approach 2:
The patent merges the test access infrastructure with the functional interconnect fabric. Instead of having separate dedicated test buses and control wiring, the design combines testing capabilities into the existing fabric structure, allowing test operations to share the same physical infrastructure as operational data flow, thereby reducing wiring congestion and area overhead.
2Adaptability or versatility
If ad-hoc Test Access Mechanisms (TAMs) are used for testing IP blocks in SoC, then testing flexibility is improved, but Time-To-Market and cost goals are jeopardized
Solution Approach 1:
By making the fabric multi-functional for both operation and testing, the patent eliminates the need for separate dedicated test infrastructure design and validation. This reuse of existing fabric reduces development time and allows for more predictable time-to-market, as the same infrastructure is validated for operational use.
Solution Approach 2:
The functional fabric serves itself by providing both operational interconnect functionality and test access capabilities through the same infrastructure. The fabric's existing control and data pathways are leveraged for testing without requiring additional dedicated test control mechanisms, reducing overall system complexity and development time.
3Reliability
If dedicated test infrastructure is used for testing IP blocks, then testing capability is improved, but gate count and wiring effort increase
Solution Approach 1:
The patent applies universality by making the functional fabric serve multiple purposes: it acts as both the operational interconnect for data transmission between IP blocks and as the test access mechanism for verification. The same fabric infrastructure is used for both normal SoC operation and testing, eliminating the need for separate dedicated test wiring and reducing overall area requirements.
Solution Approach 2:
The patent extracts the test access functionality from the traditional separate TAM infrastructure and integrates it into the functional fabric itself. By taking out the dedicated test control and access mechanisms and embedding testing capabilities within the existing fabric structure, the design reduces overall system complexity while maintaining comprehensive testing capability.
Data Source
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AI summary
A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.