Test Access Architecture for Stacked Dies via Boundary Scan
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Solution Overview
Problem
In 3-D integrated circuits, testing of through-silicon vias (TSVs) is crucial for yield enhancement, but traditional test access architectures are inefficient due to limited TSVs available for testing, as most are used for power, clock, and signal lines, necessitating a design for efficient test access and control through a small number of dedicated TSVs.
Innovation Solution
A test access architecture for stacked dies is developed, incorporating test circuitry with input and output ports for test stimuli and control, along with a data signal path, and a test access interface compatible with IEEE 1149.1, enabling efficient testing of interconnections between dies using a modular approach and boundary scan cells, allowing selective enablement/disabling of test access interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional test access architectures are used in 3-D ICs, then most TSVs are consumed for power, clock, and signal lines, but the number of TSVs available for testing becomes insufficient
Solution Approach 1:
The test access architecture is segmented into modular components including boundary scan cells integrated into individual logic blocks, multiple independent test access ports, and distributed test controllers. This segmentation allows testing functionality to be distributed throughout the 3-D IC structure rather than relying on a centralized test access mechanism that would consume excessive TSV resources.
Solution Approach 2:
The patent transitions from traditional 2-D test access approaches to 3-D test access by utilizing vertical TSV interconnects for test signal routing between stacked dies. Test access ports are distributed across multiple die layers, and boundary scan cells are integrated within 3-D logic blocks, enabling test signals to propagate through the vertical dimension of the stacked architecture rather than being constrained to planar routing.
2Ease of operation
If more TSVs are reserved for testing, then test access improves, but the keep-out area increases and fewer TSVs are available for power, clock, and signal lines
Solution Approach 1:
The boundary scan cells integrated into logic blocks serve multiple functions: they enable test access for the logic block itself, provide test access for interconnections to adjacent blocks, and can be configured for different test modes. This multi-functionality allows a single TSV to serve both functional and test purposes, eliminating the need for dedicated test-only TSVs and reducing the keep-out area.
Solution Approach 2:
Each logic block contains integrated boundary scan cells that provide self-testing capability for the block's internal logic and its interconnections. The test functionality is embedded within the functional blocks themselves, allowing them to serve their own test access needs without requiring external test resources, thereby reducing the overall TSV keep-out area required for testing.
3Reliability
If post-bond testing of TSVs is implemented, then yield increases, but test access through the bottom die becomes challenging with limited TSVs
Solution Approach 1:
Boundary scan cells are introduced as intermediary components between the TSV interconnects and the logic blocks. These boundary scan cells provide a controlled interface for test signal injection and extraction, enabling systematic testing of TSVs while managing the complexity of test access through the bottom die. The boundary scan cells act as mediators that simplify the test access path and provide standardized interfaces for post-bond testing.
4Productivity
If a modular test approach with boundary scan cells is used, then testing of interconnections between dies is enabled, but the device complexity increases
Solution Approach 1:
The boundary scan cells are merged with the functional logic blocks, combining test functionality with computational functionality in a single integrated structure. This merging eliminates the need for separate dedicated test circuits and allows the same physical resources to serve both functional and test purposes, thereby enabling efficient interconnection testing without proportionally increasing overall device complexity.
Data Source
AI summary
Aspects of the invention relate to test access architecture for stacked dies. The disclosed test access interface for a die can function as a stand-alone test access interface, allowing both pre-bond testing and post-bond testing of the die. In a stack of dies, the test access interface of a die may be enabled/disabled by the test access interface of an adjacent die.