Test Adapter for High-Speed Serial IC Testing
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Solution Overview
Problem
Conventional Automated Test Equipment (ATE) systems for integrated circuits face limitations in bandwidth, leading to increased test time and cost due to their low bandwidth cycle-by-cycle parallel interface, which restricts the ability to efficiently test larger System On Chip (SOC) devices.
Innovation Solution
A high-speed serial interface-based test adapter that decodes and interprets test data packets, routes data within the integrated circuit, and packetizes test results for transmission, utilizing a physical layer, media access control unit, and control/data unit to enhance testing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ATE with low bandwidth parallel interface is used, then device quality testing is achieved, but test time increases and test cost increases
Solution Approach 1:
The patent replaces the conventional parallel interface mechanical system with a serial interface system. The test adapter uses a serial-to-parallel conversion mechanism where serial data is received, converted to parallel data, and distributed to multiple scan chains simultaneously, achieving high-speed testing without the bandwidth limitations of traditional parallel interfaces.
Solution Approach 2:
The patent transitions from a single-dimensional parallel interface to a multi-dimensional system by implementing multiple independent scan chains that can be tested simultaneously. The test adapter receives serial data and distributes it across multiple parallel scan chains, effectively adding temporal and spatial dimensions to the testing process to increase overall bandwidth.
2Reliability
If conventional ATE with low bandwidth parallel interface is used, then device quality testing is achieved, but test cost increases
Solution Approach 1:
The test adapter is designed as a universal interface that can test multiple scan chains simultaneously using a single serial connection. This multi-functional design eliminates the need for multiple separate test equipment connections, reducing overall test system complexity and cost while maintaining comprehensive device quality testing capabilities.
Solution Approach 2:
The test adapter serves as an intermediary device between the conventional ATE and the device under test. It includes a serial-to-parallel converter that receives serial data from the ATE, converts it to parallel data, and distributes it to multiple scan chains. This intermediary approach allows existing ATE to be upgraded without replacing the entire test system, reducing cost.
3Reliability
If larger SOC devices are tested with conventional ATE, then comprehensive defect screening is achieved, but test time increases significantly
Solution Approach 1:
The patent segments the testing process into multiple independent scan chains that can operate in parallel. The test adapter receives a single serial data stream and distributes it to multiple scan chains simultaneously, allowing comprehensive defect screening across large SOC devices to be achieved through parallel processing rather than sequential testing.
Solution Approach 2:
The serial interface maintains continuous data flow to the test adapter, which continuously converts and distributes data to multiple scan chains. This continuous operation eliminates the bandwidth bottlenecks of traditional parallel interfaces and maintains high productivity throughout the testing process, enabling efficient testing of large SOC devices.
Data Source
AI summary
Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.