Test Apparatus Sampling Clock Signal Defects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing test apparatuses struggle to accurately detect defects when the clock signal is not output correctly by a device under test, particularly in source-synchronous interfaces, as they rely on the device's clock for sampling data values.
Innovation Solution
A test apparatus with a data acquiring section that can sample data signals at either the timing corresponding to the device's clock signal or a timing signal generated by the test apparatus, allowing for independent judgment of the device's pass/fail based on comparisons with expected values, and a designating section to switch between these timing modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the test apparatus uses the device under test's clock signal for sampling data, then the testing process is simple, but the apparatus cannot detect defects when the clock signal is not output correctly
Solution Approach 1:
The patent introduces an intermediary timing signal generated by the test apparatus itself, which acts as a mediator between the device under test and the sampling process. This intermediary timing signal allows the test apparatus to independently control sampling timing without relying on the device's clock signal, thereby enabling detection of clock signal defects while maintaining operational simplicity.
Solution Approach 2:
The patent implements a feedback mechanism where the test apparatus compares the sampled data against expected values and provides feedback about the sampling process. This feedback system allows the apparatus to detect whether the device under test is outputting correct clock signals and data, resolving the contradiction between simple operation and reliable defect detection.
2Device complexity
If the test apparatus relies on the device's clock signal for data sampling, then the testing procedure is straightforward, but the apparatus fails to detect defects in the clock signal output
Solution Approach 1:
The patent segments the sampling process into two independent pathways: one using the device's clock signal and another using the test apparatus's own timing signal. This segmentation allows the system to maintain simple testing procedures while adding the capability to detect clock signal defects through comparison of the two pathways.
Solution Approach 2:
The test apparatus performs preliminary action by generating its own timing signal before the actual sampling occurs. This preliminary timing signal is ready in advance and can be used to detect clock signal defects without complicating the overall testing procedure, as it operates independently and in parallel with the device's clock signal.
3Ease of operation
If the data acquiring section uses the device's clock signal for sampling, then the testing process is simple, but the apparatus cannot independently verify the clock signal timing
Solution Approach 1:
The patent introduces an intermediary timing signal that serves as an independent mediator for verification purposes. This timing signal is generated by the test apparatus itself rather than being provided by the device under test, allowing independent verification of clock signal timing while maintaining the simplicity of the testing process through the use of this neutral intermediary.
Solution Approach 2:
The patent changes the parameter of timing signal generation from device-provided to apparatus-provided. By changing this fundamental parameter, the system achieves independent timing verification without complicating the testing process, as the new timing parameter is generated internally and can be used for both sampling and verification purposes.
Data Source
AI summary
A test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, the test apparatus comprising a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to a sampling clock corresponding to the clock signal output by the device under test or a timing of a timing signal corresponding to a test period of the test apparatus; a judging section that judges pass/fail of the device under test, based on a result of a comparison between the data signal acquired by the data acquiring section and an expected value; and a designating section that designates whether the data acquiring section acquires the data signal at the timing corresponding to the sampling clock or at the timing corresponding to the timing signal.


