Test Apparatus Clock Signal Delay Adjustment
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Solution Overview
Problem
Existing source-synchronous test apparatuses face challenges in performing accurate testing due to differences in delay amounts between data and clock signal transmission paths, leading to inaccurate sampling and evaluation of device under test performance.
Innovation Solution
A test apparatus and method that utilize a bidirectional bus to synchronize data and clock signals, incorporating a test signal supplying section, data acquiring section, judging section, and adjusting section to adjust the clock signal delay, ensuring accurate sampling and comparison with expected values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data signal and clock signal are transmitted via different transmission paths, then parallel transmission is achieved, but delay mismatch occurs between the two signals
Solution Approach 1:
The patent introduces a delay adjustment mechanism as an intermediary element between the clock signal path and the data sampling point. This mediator allows precise control of the clock signal delay to match the data signal delay, compensating for the inherent delay mismatch caused by parallel transmission paths.
Solution Approach 2:
The patent changes the delay parameter of the clock signal dynamically through an adjusting section that modifies the delay amount based on measured mismatch conditions. This parameter adjustment enables the system to compensate for transmission path differences and achieve accurate sampling.
2Device complexity
If clock signal delay is fixed, then simple testing is possible, but accurate testing cannot be performed when transmission path delays differ
Solution Approach 1:
The patent segments the clock signal transmission path into controllable delay sections, allowing independent adjustment of delay parameters. This segmentation enables precise control without requiring complete system redesign, balancing complexity and reliability.
Solution Approach 2:
The patent performs preliminary delay measurement and adjustment before actual data transmission and testing. The adjusting section pre-calibrates the clock signal delay to match the data path delay, ensuring accurate testing from the start without requiring complex real-time adjustments.
3Measurement precision
If delay adjustment is implemented, then sampling accuracy is improved, but system complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the delay adjustment is based on measured delay mismatch information. The system measures the actual delay difference between data and clock paths, then uses this feedback to automatically adjust the clock delay, achieving high accuracy without requiring overly complex manual calibration systems.
Data Source
AI summary
A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired.