Test Apparatus Fail Memory Interleaving for Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor device capacity increases, the time required to transfer fail data affects test throughput, making existing test apparatuses inefficient and costly.
Innovation Solution
A test apparatus that employs a fail memory with interleave technology, a buffer memory with optional interleave technology and fewer banks, and a cache memory for faster random access, allowing for concurrent data input, test storage, and result analysis across multiple test cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacity of semiconductor devices increases, then the storage capability improves, but the transfer time of fail data increases
Solution Approach 1:
The patent divides the memory system into multiple banks (Bank 0, Bank 1, Bank 2, Bank 3) within the fail memory, allowing parallel access to different segments of stored data. This segmentation enables simultaneous read operations from multiple banks, reducing the total transfer time for large volumes of fail data while maintaining high storage capacity.
Solution Approach 2:
The patent introduces an interleave technology that adds a temporal dimension to memory access by alternating between different banks in a systematic pattern. This interleaved access pattern transforms sequential access limitations into parallel processing capabilities, effectively reducing transfer time without compromising storage capacity.
2Quantity of substance
If the transfer time of fail data increases, then the storage capacity is sufficient, but the test throughput decreases
Solution Approach 1:
The patent implements a continuous test cycle where the test executing section, fail memory, buffer memory, and analysis section operate in an uninterrupted pipeline. While one test cycle's data is being transferred and analyzed, the next test cycle can already be executed, ensuring continuous productive action without idle waiting periods, thereby maintaining high test throughput despite large data transfer requirements.
Solution Approach 2:
The fail memory is pre-configured with interleave technology and organized into multiple banks before testing begins. This preliminary preparation enables immediate parallel access to stored fail data without requiring reconfiguration during testing, allowing continuous high-speed data transfer and analysis that maintains test throughput.
3Device complexity
If a single memory is used for storing and transferring test results, then the device complexity is reduced, but the access time increases
Solution Approach 1:
Instead of using a single memory structure, the patent segments the memory system into fail memory with multiple banks and a separate buffer memory. This segmentation allows different parts of the system to perform specialized functions - the fail memory handles bulk storage with parallel access, while the buffer memory provides fast single-access operations, optimizing both capacity and speed.
Solution Approach 2:
The buffer memory acts as an intermediary between the fail memory and the analysis section. It temporarily holds data that needs rapid access during analysis operations, reducing the access time bottleneck that would occur if the analysis section directly accessed the larger fail memory without interleave optimization.
Data Source
AI summary
A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory.