Test Apparatus for High-Speed External Interface Circuit Testing
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Solution Overview
Problem
Conventional test apparatuses face difficulties in generating high-frequency test patterns for high-speed electronic devices, leading to large circuit sizes and increased costs.
Innovation Solution
A test apparatus that includes a pattern generating section to input a test pattern to an external interface circuit, an interface control section to loop back and output the test pattern, and an interface judging section to assess the acceptability of the external interface circuit, allowing for parallel testing of high-speed devices without complex logic value patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed pattern generator is used to generate test patterns at GHz range frequencies, then the testing speed matches the electronic device operational speed, but the circuit size and cost increase significantly
Solution Approach 1:
The invention divides the test apparatus into multiple functional sections: a pattern generating section that operates at lower speeds, a timing generating section that generates timing signals at the required high speed, and a waveform shaping section that combines these signals. This segmentation allows the system to achieve high-speed testing without requiring a single high-speed pattern generator, thus reducing circuit complexity.
Solution Approach 2:
The timing generating section acts as an intermediary between the low-speed pattern generator and the high-speed interface circuit. It generates timing signals at the required GHz frequencies and uses these to control when pattern bits are output, effectively mediating between the slower pattern generation and the faster interface testing requirements.
2Speed
If multiple pattern generators are provided and multiplexed to generate high-frequency test patterns, then the testing speed increases, but the circuit size becomes undesirably large
Solution Approach 1:
The invention uses a dynamic approach where a single pattern generator operates at lower speed but is controlled by high-speed timing signals. The timing generating section dynamically controls the output timing of pattern bits, allowing the system to achieve high-frequency testing capabilities without the static overhead of multiple parallel pattern generators.
Solution Approach 2:
The timing generating section serves multiple functions: it generates timing signals for the pattern generator, controls the waveform shaping section, and synchronizes the overall testing process. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall circuit size while maintaining high-speed capabilities.
3Ease of manufacture
If conventional algorithm pattern generators are used, then the circuit design is simple, but they cannot operate at high frequencies in the GHz range
Solution Approach 1:
The invention replaces the requirement for a high-speed mechanical/electronic pattern generator with a combination of a low-speed pattern generator and a timing signal-based control system. The timing signals effectively 'substitute' for the high-speed operation requirement, allowing conventional low-speed pattern generators to achieve high-speed testing through proper timing control.
Data Source
AI summary
Provided is a test apparatus that tests a device under test including an external interface circuit that transfers signals between an internal circuit inside a device and the outside of the device, the test apparatus comprising a pattern generating section that inputs, to the external interface circuit, a test pattern for testing the external interface circuit; an interface control section that causes the external interface circuit to loop back and output the test pattern; and an interface judging section that judges acceptability of the external interface circuit based on the test pattern looped back and output by the external interface circuit.