Test Apparatus for Semiconductor Jitter Reduction via Time Interval Measurement
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Solution Overview
Problem
Test apparatuses struggle to accurately assess semiconductor devices due to jitter and drift in data signals, leading to false defects in non-defective products when using asynchronous testing methods.
Innovation Solution
A test apparatus with a time measurement unit to measure intervals between signal edges and a comparison judgment unit to calculate and compare the number of bits, capable of reducing jitter and drift effects by rounding non-integer values and generating a Pass/Fail signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a test apparatus performs asynchronous operation with the DUT to simplify the testing interface, then device complexity is reduced, but measurement precision deteriorates due to phase shifts exceeding 1 UI caused by jitter and drift
Solution Approach 1:
The patent introduces a time measurement unit as an intermediary component that measures the time interval between edges in the signal under test. This mediator captures the actual timing information including jitter and drift, allowing the system to compensate for phase shifts without requiring a complex clock recovery circuit. The time measurement unit acts as a bridge between the asynchronous test apparatus and the DUT, enabling accurate measurement while maintaining interface simplicity.
2Measurement precision
If the test apparatus includes a clock recovery circuit to synchronize with the DUT, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent extracts the essential timing measurement function from a full clock recovery circuit. Instead of implementing a complete clock recovery system that would synchronize the entire test apparatus, the invention only extracts the critical function of measuring time intervals between signal edges. This selective extraction maintains measurement precision by capturing timing information while avoiding the complexity of full clock synchronization hardware.
Solution Approach 2:
The patent employs a simplified timing measurement approach that uses basic time interval measurement rather than expensive, complex clock recovery circuits. The solution uses readily available time measurement capabilities to capture edge timing information, providing an cost-effective alternative to sophisticated synchronization systems while achieving the necessary measurement accuracy.
3Measurement precision
If the test apparatus uses rounding to handle non-integer bit counts, then measurement precision improves by reducing jitter effects, but loss of information occurs through rounding non-integer values
Solution Approach 1:
The patent converts the harmful effect of jitter and drift into a beneficial measurement approach. By measuring the actual time interval between edges and calculating the corresponding bit count, the system captures the true signal characteristics including jitter. The rounding operation then serves to normalize these measurements into meaningful integer bit counts, transforming the continuous timing variations into discrete, analyzable data that reflects actual signal behavior rather than idealized expectations.
Data Source
AI summary
A time measurement unit measures the time interval between edges to be monitored in a signal under test DUT_Output including serial data output from a device under test (DUT) 400. A comparison judgment unit calculates the number of bits of the serial data included between the edges to be monitored, based on the time interval thus measured. Furthermore, the comparison judgment unit compares the number of bits thus calculated with an expected value thereof.