Test Apparatus Pattern Selecting Unit for PLL Lock Maintenance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing test apparatuses face challenges in maintaining the locked state of PLL/DLL circuits during test condition switching, especially when using embedded-clock methods like CDR or packet methods, as the clock signal is not continuously supplied, leading to prolonged test times.
Innovation Solution
A test apparatus with a pattern selecting unit that generates and manages different output modes, including a mode to supply a synchronization pattern during vector pattern cessation, and a mode to continuously output a clock signal, ensuring the PLL/DLL circuit remains locked across test condition changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the supply of clock signal to DUT is stopped during test condition switching, then test condition switching can be performed, but the PLL/DLL circuit switches from locked state to unlocked state, requiring re-locking time
Solution Approach 1:
The patent applies preliminary action by continuously supplying a clock signal during test condition switching before the actual test pattern is supplied. This keeps the PLL/DLL circuit in the locked state in advance, so when testing resumes, no re-locking time is needed. The clock signal supply is maintained during the switching period to prevent the circuit from unlocking.
2Reliability
If a clock signal is continuously output to the clock input pin during test condition switching, then the PLL/DLL circuit remains in locked state, but this method is incompatible with embedded-clock methods where clock signal is embedded in data signal
Solution Approach 1:
The patent applies dynamics by making the signal output mode adaptable and changeable. The test apparatus can dynamically switch between different output modes: for traditional interfaces, it outputs continuous clock signal; for embedded-clock interfaces like CDR or packet methods, it outputs synchronization patterns that contain embedded clock information. This dynamic adaptation allows compatibility with different interface types while maintaining locked state.
Solution Approach 2:
The patent changes the parameter of the output signal from a simple clock signal to a synchronization pattern that embeds clock information. By modifying the signal characteristics to include synchronization patterns with embedded clock signals, the system maintains compatibility with embedded-clock methods while still providing the necessary clock information to keep the PLL/DLL circuit locked.
3Reliability
If synchronization pattern is supplied during vector pattern cessation in embedded-clock methods, then locked state can be maintained, but requires additional pattern generating unit and control logic
Solution Approach 1:
The patent applies universality by designing a pattern selecting unit that can handle multiple types of patterns (vector patterns, synchronization patterns, idle patterns) and switch between them based on the interface type. This multi-functional unit replaces the need for separate dedicated circuits for different interface types, reducing overall system complexity while maintaining the ability to supply appropriate patterns for locked state maintenance.
Data Source
AI summary
A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated.