Test Apparatus Relay Section Interrupt Handling
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Solution Overview
Problem
Current test apparatuses face inefficiencies in detecting state changes of test units, leading to increased computing power requirements for control processors, resulting in higher costs and failure rates due to the need for multiple processors and complex designs, especially when trying to quickly and accurately detect state changes.
Innovation Solution
A test apparatus with a relay section that includes a polling section to repeatedly read a status register and a process control section to send control instructions after the register reaches an expected value, along with a buffer section to manage commands, allowing for efficient timing control and reduced processing load on the control processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polling is used to detect state changes, then state detection is simple to implement, but computing power is wasted due to long time distances between reads
Solution Approach 1:
An interrupt handler is introduced as an intermediary between the test unit and control processor. The interrupt handler detects state changes and triggers interrupts, eliminating the need for continuous polling while maintaining simple implementation. This resolves the contradiction by providing efficient state detection without wasting computing power.
Solution Approach 2:
The test unit is enabled to autonomously detect its own state changes and generate interrupts when state transitions occur. This self-service mechanism eliminates the need for external polling, allowing the control processor to focus on other tasks while the test unit independently monitors its state, thus improving computing power utilization.
2Speed
If interrupt handling is implemented, then state detection speed increases, but system design becomes complicated and processing load increases
Solution Approach 1:
A universal interrupt handling mechanism is provided that can be shared across multiple test units through the common bus. Instead of implementing separate interrupt mechanisms for each test unit, the system uses a single interrupt handler that processes interrupts from any test unit, reducing design complexity while maintaining fast state detection.
Solution Approach 2:
The interrupt handler serves as an intermediary that simplifies the interface between test units and the control processor. It abstracts the complex interrupt handling logic into a single component that can be easily configured and maintained, reducing overall system design complexity while enabling fast state detection.
3Reliability
If multiple control processors are mounted to handle state detection, then detection capability increases, but apparatus size and cost increase
Solution Approach 1:
The interrupt handling mechanism is designed to be universal and shared across multiple test units. A single control processor can handle interrupts from multiple test units through the common bus, eliminating the need for dedicated control processors for each test unit. This maintains high state detection capability while reducing apparatus size and complexity.
Solution Approach 2:
Multiple interrupt handling functions are merged into a single interrupt handler that processes state changes from all test units. By combining these functions, the system achieves comprehensive state detection capability with a single control processor, avoiding the need for multiple processors and reducing overall apparatus size.
Data Source
AI summary
There is provided a test apparatus that tests a device under test. The test apparatus includes a control processor that executes a test program for testing the device under test, a test unit that is connected to the device under test and tests the device under test according to an instruction from the control processor, and a relay section that is connected to the control processor and the test unit and relays a control instruction sent from the control processor to the test unit. The relay section includes a polling section that repeatedly reads a status register showing a state of the test unit, which is designated by the control processor, and a process control section that sends the control instruction to be processed by the test unit after a value of the status register becomes an expected value to the test unit according to the fact that the value of the status register becomes the expected value designated by the control processor.