Test Bench Hierarchy Visualization for Debugging Connectivity

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Solution Overview

Problem

In electronic design automation, debugging microdevice circuits is hindered by incomplete understanding of test bench hierarchy and connectivity, particularly due to reliance on standardized components and transient object-oriented programming languages, which can lead to misidentification of bugs in circuit designs or test benches.

Innovation Solution

A design verification tool identifies library components in the test bench, inserts connection calls, and captures messages to generate a schematic representation of the test bench, allowing a debug tool to display a hierarchical or connectivity representation, facilitating the isolation of bugs by providing a clear view of test bench functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If standardized components and transient object-oriented programming languages are used to build test benches, then test bench development efficiency is improved, but understanding of test bench hierarchy and connectivity deteriorates

Engineering Contradiction:

Improvetest bench development efficiencyVSAvoidunderstanding of test bench hierarchy and connectivity

Core Design Contradiction:

ProductivityVSLoss of information

Solution Approach 1:

The patent creates a visual schematic representation that copies and displays the hierarchical structure and connectivity information of the test bench. This schematic serves as a visual copy of the abstract object-oriented code, making the hierarchy and connections visible and understandable without requiring developers to manually trace through transient code structures.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent introduces an intermediary tool that translates between the object-oriented programming language and a visual schematic representation. This intermediary captures connectivity information from the code and presents it in a human-readable format, bridging the gap between efficient code-based test bench creation and understandable structural representation.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of time

If debugging is performed without clear test bench hierarchy representation, then debugging speed may be improved through direct code analysis, but debugging accuracy deteriorates due to misidentification of bugs

Engineering Contradiction:

Improvedebugging speedVSAvoiddebugging accuracy

Core Design Contradiction:

Loss of timeVSMeasurement precision

Solution Approach 1:

The patent segments the test bench structure into hierarchical levels that can be independently analyzed. By dividing the complex test bench into manageable hierarchical segments, developers can quickly locate and analyze specific portions without being overwhelmed by the entire codebase, maintaining both speed and accuracy in bug identification.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8782581B2Test bench hierarchy and connectivity in a debugging environment

Publication Date: 2014.07.15 SIEMENS INDUSTRY SOFTWARE INC

AI summary

This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding to at least portions of the library components, which are interconnected with trace lines based, at least in part, on the messages. The debug tool can prompt display of the schematic representation of the test bench.