Test Bench Transaction Synchronization for Debugging Circuit Designs
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Solution Overview
Problem
In electronic design automation, synchronizing simulated output from a circuit design with test bench transactions is challenging due to the transient nature of object-oriented programming languages, leading to difficulties in collating test bench states and transitions with waveform data, making it hard to determine whether verification failures are due to circuit design bugs or test bench defects.
Innovation Solution
A design verification tool simulates a circuit design with a test bench, generating a simulation log that synchronizes simulated output with test bench transactions, allowing a debug tool to associate test bench transactions with waveform data and source code, facilitating the identification of defects in both the circuit design and the test bench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If test bench transactions are implemented using object-oriented programming languages, then the test bench can be dynamically created and configured, but the transient nature of these languages makes it difficult to collate test bench states and transitions with waveform data
Solution Approach 1:
The patent applies preliminary action by having the design verification tool automatically generate and store test bench transaction data in a structured format during the simulation process. This pre-prepared data includes transaction identifiers, timestamps, and state information that can be directly correlated with waveform data later, eliminating the need to manually track transient object-oriented states.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a simulation log that captures test bench transactions and their states. This log serves as a mediator between the transient object-oriented test bench and the waveform data, allowing designers to correlate transactions with waveforms through the logged information without directly accessing the transient program states.
2Ease of operation
If manual collation of test bench states and waveform data is performed, then flexibility in analysis is maintained, but the process becomes time-consuming and error-prone
Solution Approach 1:
The patent applies self-service by enabling the design verification tool to automatically perform the collation and correlation of test bench transactions with waveform data. The tool generates structured logs during simulation and provides built-in functionality to match transactions with corresponding waveforms, eliminating the need for manual, time-consuming collation processes while maintaining analysis flexibility.
Solution Approach 2:
The patent implements feedback mechanisms where the design verification tool automatically compares simulated output with expected output and provides correlated feedback information. When mismatches are detected, the tool uses the logged transaction data to immediately identify which specific test bench transaction caused the failure, providing rapid feedback without manual intervention.
3Reliability
If test bench transactions are executed dynamically, then verification coverage is improved, but it becomes difficult to determine whether verification failures are due to circuit design bugs or test bench defects
Solution Approach 1:
The patent applies segmentation by breaking down test bench transactions into discrete, identifiable units with unique identifiers and state information. Each transaction is logged separately with its specific parameters and expected outcomes, allowing failures to be traced back to individual transactions rather than appearing as undifferentiated errors in dynamic execution.
Solution Approach 2:
The patent uses feedback by automatically comparing the actual simulated output with the expected output for each test bench transaction. When a failure occurs, the system provides correlated feedback that includes the transaction identifier, state information, and waveform data, enabling immediate determination of whether the failure stems from the circuit design or the test bench itself.
Data Source
AI summary
This application discloses a design verification tool to simulate a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design. The design verification tool can determine whether the simulated output for the circuit design is different than an expected output for the circuit design. A debug tool can synchronize the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.