Semiconductor Package Test Bump Arrangement for Stacking Defect Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in reliably detecting stacking defects such as open failure and short failure between semiconductor chips, which can lead to operational issues during the reliability evaluation and customer use, despite initial tests showing no failures.
Innovation Solution
Incorporating first and second test bumps adjacent to each other on the semiconductor chips, with specific intervals between them and the data bumps, allowing for effective detection of open and short failures by a controller that supplies test signals to determine the correct stacking state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional semiconductor package stacking is used, then manufacturing simplicity is maintained, but reliability is reduced due to undetected stacking defects
Solution Approach 1:
The bump structure is segmented into three distinct types: first test bumps, second test bumps, and data bumps. This segmentation allows each type to serve specific functions - test bumps for detecting open/short failures and data bumps for normal data transmission, thereby improving reliability without compromising manufacturing simplicity
Solution Approach 2:
Test bumps are preliminarily arranged in specific patterns (first test bumps at corners, second test bumps at edge centers) before actual stacking occurs. This preliminary arrangement enables pre-stacking verification of stacking alignment and detection of potential defects, allowing corrective actions to be taken before final product assembly
2Reliability
If test bumps are added to detect stacking defects, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The test bumps serve multiple functions: detecting open failures, detecting short failures, and verifying stacking alignment. By consolidating these detection functions into a single test bump structure with specific arrangements, the patent avoids needing separate test structures for each function, thereby maintaining ease of manufacture while achieving comprehensive defect detection
Solution Approach 2:
The test bump structure is a simplified copy of the data bump structure, using the same basic bump geometry and materials but arranged in specific test patterns. This copying approach allows the manufacturing process to remain largely unchanged while adding detection capability, as the same bump fabrication processes are used for both test and data bumps
Data Source
AI summary
Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.