Test Bump Vertical Profile for Die Testing Shorting
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Solution Overview
Problem
The existing methods for die testing using solder bumps face challenges such as shorting and increased complexity due to the proximity of test bumps to die bumps, especially with shrinking solder bump pitch, requiring the removal of adjacent die bumps to avoid connections with the wafer probe, which affects efficiency and performance.
Innovation Solution
The solution involves forming test bumps with a taller vertical profile than die bumps, using techniques like die pressing, force compression, or customized masking to prevent shorting during testing, allowing for uniform pitch between solder bumps without removing adjacent die bumps, and enabling efficient on-chip circuit placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test bumps are formed with standard geometry same as die bumps, then manufacturing process is simple, but wafer probe shorts occur during testing due to proximity of test bumps to die bumps
Solution Approach 1:
The patent applies local quality by giving test bumps a distinct taller vertical profile compared to die bumps. This local differentiation in geometry allows the wafer probe to make contact with test bumps without shorting to adjacent die bumps, thereby improving testing reliability while maintaining overall process simplicity
Solution Approach 2:
The patent introduces a vertical dimension differentiation between test bumps and die bumps. By making test bumps taller in the vertical direction while maintaining the same planar pitch, the invention creates a three-dimensional distinction that enables reliable probing without shorting, effectively using dimensional change to resolve the contradiction
2Reliability
If adjacent die bumps are removed to avoid shorting during testing, then shorting is prevented, but manufacturing complexity increases and die bump density decreases
Solution Approach 1:
Instead of removing die bumps, the patent modifies only the local geometry of test bumps by making them taller. This localized change prevents shorting during testing while preserving all die bumps, thereby maintaining manufacturing simplicity and die bump density while achieving reliable testing
Solution Approach 2:
The patent applies preliminary action by forming test bumps with a taller vertical profile during the bump formation process itself, before the testing stage. This pre-established geometric differentiation ensures that no shorting will occur during subsequent probing, eliminating the need for post-formation die bump removal
3Quantity of substance
If solder bump pitch is reduced to increase die density, then die density improves, but risk of shorting during testing increases due to closer proximity of test bumps to die bumps
Solution Approach 1:
The patent uses vertical dimension differentiation to resolve the contradiction enabled by reduced pitch. By making test bumps taller while maintaining uniform pitch, the invention allows closer spacing of bumps (increasing die density) while preventing shorting through the vertical clearance created by the taller test bump profile
Solution Approach 2:
The patent applies local quality by differentiating test bump geometry from die bump geometry. This local distinction in vertical profile allows the system to maintain high die density with reduced pitch while ensuring that probing operations do not cause shorting, as the taller test bumps provide isolated contact points
Data Source
AI summary
A semiconductor chip may include a die having one or more circuits. The semiconductor chip may include a plurality of die bumps, each having a first geometry, a first vertical profile, and a first volume. The die bumps may be coupled to the die and in electrical communication with the one or more circuits. The semiconductor device may include a plurality of test bumps each having a second geometry, a second vertical profile, and the first volume. The test bumps may be coupled to the die and in electrical communication with the one or more circuits. The first geometry and the second geometry may be adapted for the plurality of test bumps to make connection with a wafer probe to the test bumps without making a connection to any of the die bumps during a die test.