Test Carrier Segmented Interconnect Patterns Ink Jet Printing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing test carriers face challenges in handling numerous types of semiconductor chips due to difficulties in productivity when forming interconnect patterns, particularly when using ink jet printing.
Innovation Solution
A test carrier design featuring a first member with pre-formed conduction paths and a second member with a printing region for forming additional conduction paths via ink jet printing, allowing for real-time adaptation to various electronic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching copper foil to form interconnect patterns is used, then manufacturing precision is improved, but adaptability deteriorates
Solution Approach 1:
The interconnect pattern formation process is segmented into two distinct parts: pre-formed patterns (first interconnect patterns) and dynamically printed patterns (second interconnect patterns). This segmentation allows the test carrier to combine the precision of etching with the flexibility of ink jet printing, resolving the contradiction between manufacturing precision and adaptability.
Solution Approach 2:
The first interconnect patterns are formed in advance through etching copper foil, establishing a precise baseline structure. This preliminary action allows the subsequent ink jet printing to focus only on adding specific variations, maintaining precision while enabling adaptability across different chip types.
2Adaptability or versatility
If ink jet printing is used to form interconnect patterns in real time, then adaptability is improved, but productivity deteriorates
Solution Approach 1:
The interconnect pattern formation is divided into pre-formed patterns and printed patterns. By segmenting the work, the ink jet printing only needs to add the variable second interconnect patterns rather than forming complete patterns, significantly reducing printing time and improving productivity while maintaining adaptability.
Solution Approach 2:
Instead of printing complete interconnect patterns, the system performs partial action by only printing the second interconnect patterns that need to be added to the pre-formed first interconnect patterns. This partial action reduces printing time and improves productivity while still achieving the required adaptability.
3Adaptability or versatility
If a single test carrier is used to handle numerous types of semiconductor chips, then adaptability is improved, but the complexity of forming interconnect patterns increases
Solution Approach 1:
The complex task of forming complete interconnect patterns for various chip types is segmented into a simple pre-formation step (first interconnect patterns) and a flexible addition step (second interconnect patterns). This segmentation reduces the complexity of the overall process while maintaining the ability to handle numerous chip types.
Solution Approach 2:
The test carrier is designed with universal first interconnect patterns that can serve as a base for multiple different chip types. The ink jet printing capability adds specific second interconnect patterns as needed, making the single test carrier universally applicable to numerous electronic device types without increasing overall process complexity.
Data Source
AI summary
A test carrier includes a base member and a cover member between which a die is interposed. The base film of the base member has: first interconnect patterns which are formed in advance; and a printing region where second interconnect patterns which electrically connect to the first interconnect patterns are to be formed by printing.