Test Circuit Asynchronous Register Prevents Unknown Values

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Solution Overview

Problem

Existing test circuits face challenges in transmitting test signals effectively under an at-speed clock, leading to the generation of unknown values that reduce test performance.

Innovation Solution

A test circuit and method utilizing a first wrapper chain and a scan chain, with asynchronous registers to prevent unknown values during the capture phase by shifting and transmitting test patterns according to specific clocks, ensuring accurate data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an at-speed clock is used to simulate real circuit operation during testing, then the realism of the test is improved, but unknown values are generated due to timing issues, reducing test performance

Engineering Contradiction:
Improvetest performanceVSAvoidunknown values
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The test circuit is segmented into multiple wrapper chains (first wrapper chain and second wrapper chain) with separate clock domains. The first wrapper chain uses a first clock for shifting test patterns, while the second wrapper chain uses a second clock for capturing results. This segmentation allows each chain to operate independently without timing conflicts, preventing unknown values while maintaining at-speed testing capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A scan chain is introduced as an intermediary between the first and second wrapper chains. The scan chain receives test patterns from the first wrapper chain and transmits them to the circuit under test, while also capturing results and transmitting them back. This intermediary structure decouples the timing requirements of the two wrapper chains, allowing them to operate at different clock speeds without interfering with each other.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If the circuit device transmits test signals in real time under at-speed clock, then the test speed is improved, but transmission accuracy deteriorates due to timing issues

Engineering Contradiction:
Improvetest speedVSAvoidsignal transmission accuracy
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The test circuit dynamically switches between different operational phases (scan-in phase, capture phase, scan-out phase) with different timing requirements. During scan-in phase, the first wrapper chain operates at a slower first clock speed to ensure accurate signal transmission. During capture phase, the second wrapper chain operates at the at-speed second clock to achieve high-speed testing. This dynamic phase-based operation allows the system to optimize for both accuracy and speed at different times.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If asynchronous registers are added to prevent unknown values, then test accuracy is improved, but circuit complexity increases

Engineering Contradiction:
Improvetest accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The wrapper cells in the first and second wrapper chains are designed to be multi-functional, serving both as shift registers during scan-in phase and as capture registers during capture phase. The scan chain also serves dual purposes: transmitting test patterns forward and capturing results backward. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in circuit complexity while still achieving improved test accuracy through proper timing control.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11988711B2Test circuit and test method
Publication Date: 2024.05.21 REALTEK SEMICON CORP
  • US11988711B2 patent drawing
  • US11988711B2 patent drawing
  • US11988711B2 patent drawing

AI summary

A test circuit includes a scan chain and a wrapper chain. The wrapper chain shifts in a test pattern according a first clock. The scan chain is coupled to the wrapper chain via a logic combination of a circuit under test. The wrapper chain is configured to transmit the test pattern to the scan chain via the logic combination according to a second clock in a capture phase. The wrapper chain includes a first, a second wrapper cell, and an asynchronous register. The first wrapper cell sequentially shifts in two bits of the test pattern in the shift-in phase. The second wrapper cell shifts in the first bit of the test pattern in the shift-in phase. The asynchronous register conducts the first wrapper cell to the second wrapper cell in the shift-in phase, and latches the second wrapper cell in the capture phase.