Test Circuit for Dynamic BIST and Functional Clock Path Fault Detection
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Solution Overview
Problem
Existing test circuits face challenges in simultaneously testing built-in self test (BIST) and functional clock and data paths during scan testing due to congestion on the clock path and inability to detect faults on both paths effectively, leading to increased complexity and time in identifying failure sources.
Innovation Solution
A test circuit with separate clock generators for BIST and functional logic, a multiplexer to selectively pass clocks based on a clock selection signal, and a clock selection circuit that dynamically switches between BIST and functional clocks during scan testing, allowing faults on both clock and data paths to be checked in a single pass.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single clock signal is used for both BIST logic and functional logic, then timing requirements for scan testing are met, but clock path congestion occurs and fault detection capability is reduced
Solution Approach 1:
The patent divides the clock distribution system into separate clock trees: a first clock tree for BIST logic and a second clock tree for functional logic. This segmentation allows independent clock path management, eliminating congestion while maintaining timing requirements. Each clock tree can be independently optimized and tested without interfering with the other.
Solution Approach 2:
The patent introduces a multiplexer as an intermediary device that selectively switches between BIST mode clock signals and functional mode clock signals. This intermediary allows dynamic clock source selection based on operational mode, enabling both BIST and functional logic to receive appropriate clock signals without direct congestion on shared paths.
2Device complexity
If separate clock trees are used for BIST and functional logic, then clock path congestion is eliminated, but fault detection on both clock paths becomes more complex
Solution Approach 1:
The patent merges the BIST and functional scan chains into a unified scan chain structure that can operate in both BIST mode and functional mode. This merging allows a single test pattern to traverse both clock paths sequentially, detecting faults on both BIST clock tree and functional clock tree without requiring separate complex test structures.
Solution Approach 2:
The patent implements dynamic mode switching capability where the same scan chain and test equipment can dynamically transition between BIST mode and functional mode operation. The multiplexer dynamically switches clock sources based on mode, and the scan chain dynamically reconfigures connections, allowing flexible fault detection across both clock paths using a unified testing approach.
3Speed
If BIST and functional logic are balanced to operate with the same clock, then timing requirements are met, but the ability to independently test clock paths is lost
Solution Approach 1:
The patent segments the clock distribution into separate trees while maintaining timing balance within each tree. The first clock tree is optimized for BIST logic timing requirements, and the second clock tree is optimized for functional logic timing requirements. This segmentation preserves independent testing capability while meeting respective timing constraints.
Solution Approach 2:
The patent creates a universal scan chain structure and test methodology that can perform both BIST mode testing and functional mode testing. The same test equipment and scan chain infrastructure serve multiple functions: testing BIST logic with BIST clock, testing functional logic with functional clock, and detecting faults on both clock paths, thereby achieving multi-functionality without sacrificing timing performance.
Data Source
AI summary
A test circuit includes a BIST clock generator and a functional clock generator. A first multiplexer selectively passes the BIST clock or the functional clock as a selected clock in response to a clock selection signal. BIST logic operates based upon the BIST clock. Functional logic operating based upon the functional clock signal. A memory operates based upon the selected clock. When the test circuit is operating in BIST mode, a clock selection circuit receives and passes a BIST signal as the clock selection signal. When the test circuit is operating in a shift phase of a scan test mode, it generates the clock selection signal as asserted, and when the test circuit is operating in the capture phase of the scan test mode, it generates the clock signal as equal to a last bit received from a scan chain.