Test Circuit Clock Gating Single Multiplexer Bypass

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Solution Overview

Problem

Existing test circuits for integrated circuits face challenges in efficiently isolating specific cores or circuits during testing, as they often require multiple multiplexers and complex feedback loops to manage clock signals and capture procedures.

Innovation Solution

A test circuit that utilizes a single multiplexer in bypass mode to transmit cell function inputs to outputs, combined with a clock gating scheme to control the capture procedure, thereby reducing transmission delays and enhancing fault detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple multiplexers and complex feedback loops are used to manage clock signals and capture procedures, then the test circuit can maintain signal integrity and control capture timing, but the device complexity and transmission delays increase

Engineering Contradiction:

Improvesignal integrity and capture timing controlVSAvoidnumber of multiplexers and feedback loops

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the feedback loop mechanism from the test circuit design. By removing the feedback path that previously connected the capture output back to the multiplexer select control, the circuit simplifies the signal path while maintaining functional integrity through alternative control mechanisms using dedicated test mode signals

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements a universal test control mechanism where a single multiplexer handles both normal operation data selection and test mode capture operations. The multiplexer is controlled by a unified test mode signal that directs it to different input sources (normal data vs. capture data) based on operational mode, eliminating the need for separate control paths

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple multiplexers are used in the test circuit, then signal routing flexibility is improved, but transmission delays increase

Engineering Contradiction:

Improvesignal routing flexibilityVSAvoidtransmission delays

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent merges the functions of multiple multiplexers into a single multiplexer that handles all data selection tasks. By consolidating the data path control into one multiplexer stage, the circuit reduces the cumulative transmission delay that would result from passing signals through multiple multiplexer stages, while maintaining routing flexibility through comprehensive select signal control

Inventive Principle:

Principle #5Merging (Combining)

3Measurement precision

If complex feedback loops are used to control capture procedures, then capture timing precision is improved, but the device complexity increases

Engineering Contradiction:

Improvecapture timing precisionVSAvoidcomplexity of feedback loops

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a dedicated test mode control signal as an intermediary that directly controls the multiplexer selection during capture operations. This intermediary signal replaces the need for complex feedback loop control logic, providing precise timing control through a simple, direct control path that activates the capture function without requiring sophisticated feedback mechanisms

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentEP4180825B1Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same

Publication Date: 2025.04.16 SAMSUNG ELECTRONICS CO LTD

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AI summary

Disclosed is a test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core. The test circuit may not only transmit a cell function input to a cell function output using only one multiplexer in a bypass mode, may but also use a clock gating scheme capable of blocking a clock signal from transmitting to a scan flip-flop to hold a capture procedure.