Test Circuit Clock Gating Bypass Mode Isolation
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Solution Overview
Problem
Existing test circuits for integrated circuits face challenges in efficiently isolating specific cores during testing, as they require electrical isolation from peripheral circuits and must prevent output values from affecting the system, while also needing to transmit cell function inputs to outputs effectively.
Innovation Solution
A test circuit that utilizes a bypass mode with a single multiplexer to transmit cell function inputs and incorporates a clock gating scheme to control the capture procedure, allowing for the isolation of cores and external circuits, reducing transmission delays and enhancing fault detection by using a clock gating circuit to manage clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test circuit uses traditional isolation methods for cores during testing, then electrical isolation from peripheral circuits is achieved, but transmission delay increases and timing margins are reduced
Solution Approach 1:
The patent introduces a wrapper circuit as an intermediary layer between the core and peripheral circuits. This wrapper includes multiplexers and clock gating circuits that mediate signal transmission, enabling both electrical isolation and maintained timing performance. The wrapper acts as a buffer that prevents direct interference while preserving signal integrity and timing characteristics.
2Adaptability or versatility
If a test circuit uses multiple multiplexers for signal transmission, then signal routing flexibility is improved, but device complexity increases
Solution Approach 1:
The patent designs the wrapper circuit with universal multiplexers that can operate in multiple modes (bypass mode and capture mode). The same multiplexer structure handles both normal signal transmission and test signal routing, eliminating the need for separate dedicated multiplexers for different functions. This multi-functionality reduces overall device complexity while maintaining routing flexibility.
Solution Approach 2:
The patent combines the bypass function and capture function into a single integrated wrapper circuit structure. Instead of using separate circuits for bypass mode and capture mode, the design merges these functions into one unified wrapper that can dynamically switch between modes using control signals, thereby reducing the total number of components and simplifying the overall circuit architecture.
3Measurement precision
If a test circuit captures all signals during testing, then fault detection coverage is improved, but timing risks increase due to capture procedure overhead
Solution Approach 1:
The patent implements dynamic clock gating control where the clock signal to the capture circuitry is enabled only when actually needed for fault detection. The clock gating circuit responds to control signals that activate capturing only during specific test phases or when fault conditions are suspected, rather than continuously capturing all signals. This dynamic approach maintains high fault detection coverage while minimizing the time overhead associated with continuous capture operations.
Data Source
AI summary
Disclosed is a test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core. The test circuit may not only transmit a cell function input to a cell function output using only one multiplexer in a bypass mode, may but also use a clock gating scheme capable of blocking a clock signal from transmitting to a scan flip-flop to hold a capture procedure.