Test Circuit Clock Path Selection for Semiconductor Yield
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Solution Overview
Problem
In semiconductor devices with stacked chips, failures in signal paths due to manufacturing defects, such as open microbumps or short-circuits, lead to decreased yield ratios and increased costs, particularly when the clock path fails, making it difficult to operate scan flip-flops and detect failure sites.
Innovation Solution
A test circuit with a clock detection unit and clock path selection unit that redundantly transmits test clocks through multiple paths, allowing the detection and bypassing of failure sites, even if one clock path fails, thereby improving yield ratios and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single clock path is used to transmit test clocks between semiconductor chips, then the device complexity is reduced, but the reliability of test operations decreases when manufacturing defects occur
Solution Approach 1:
The clock transmission path is segmented into multiple independent paths (first clock path and second clock path) between the semiconductor chips. This allows the test system to switch between different paths if one path fails due to manufacturing defects, thereby maintaining test operation reliability without significantly increasing overall device complexity
Solution Approach 2:
The test circuit performs preliminary detection of clock paths before actual testing. The clock path detection function identifies functional clock paths in advance, allowing the system to select valid paths before test operations begin, ensuring reliable test operations while managing device complexity through proactive path validation
2Measurement precision
If scan flip-flops are used to detect failure sites in signal paths, then the measurement precision of failure detection is improved, but the ease of operation decreases when clock paths fail
Solution Approach 1:
The invention introduces a clock path detection function as an intermediary between the test clock source and the scan flip-flops. This intermediary detects and validates clock paths before test operations, ensuring that scan flip-flops receive proper clock signals and can operate effectively for failure detection without manual intervention when clock paths fail
3Reliability
If multiple clock paths are provided for redundant transmission, then the reliability of test operations is improved, but the device complexity increases
Solution Approach 1:
The clock transmission system is segmented into multiple independent clock paths (first and second clock paths) that can be selectively activated. This segmentation provides redundancy for reliable test operations while keeping each individual path relatively simple, balancing reliability improvement with manageable device complexity
Solution Approach 2:
The test circuit dynamically selects and switches between different clock paths based on their operational status. The clock path selection function adapts to the actual state of clock paths, activating only the necessary functional paths during test operations, thereby providing redundancy when needed while minimizing device complexity during normal operation
Data Source
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AI summary
A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.