Test Circuit Data Masking for Semiconductor Pin Reduction
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Solution Overview
Problem
Conventional semiconductor integrated circuits face limitations in parallel testing due to the restricted number of data I/O pins, which increases testing time and reduces test efficiency, especially when transitioning from X16 to X8 I/O mode, making it harder to detect pin failures.
Innovation Solution
A test circuit with a data masking control unit that masks upper and lower data pins during read operations using upper and lower data masking signals, allowing the circuit to operate as if in an X8 I/O mode even when internally configured for X16, thereby reducing the number of I/O pins needed and increasing parallel testing capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of data I/O pins is increased to test more circuits in parallel, then testing capacity is improved, but the cost and complexity of the tester increases
Solution Approach 1:
The data I/O pins are segmented into upper and lower groups, with separate masking control applied to each group. This allows independent control of data transmission on different pin sets, enabling the same physical pins to serve multiple testing functions and increase parallel testing capacity without adding more physical pins.
Solution Approach 2:
The data masking control unit dynamically adjusts which data pins are active during read operations based on control signals. By dynamically masking upper or lower data pins, the system can flexibly reconfigure pin allocation for different test scenarios, effectively increasing testing capacity without permanent hardware additions.
2Device complexity
If the number of data I/O pins is reduced to lower tester cost, then device complexity is reduced, but the number of circuits that can be tested in parallel decreases
Solution Approach 1:
The same set of data I/O pins is made multi-functional through the data masking control unit. By selectively masking upper or lower data pins during read operations, the same physical pins can serve different testing purposes, allowing the system to maintain high testing capacity with fewer physical pins.
Solution Approach 2:
The data masking control unit applies periodic masking patterns to upper and lower data pins during read operations. This periodic activation and deactivation of different pin groups allows the system to efficiently utilize limited pins for multiple circuits, maintaining high testing capacity without increasing pin count.
3Productivity
If data masking is applied during read operation, then the number of active data pins is reduced, but the ability to detect pin failures may be compromised
Solution Approach 1:
The data masking control unit applies masking signals before actual data read operations. This preliminary masking allows the system to prepare the correct pin configuration in advance, ensuring that only necessary pins are active during each operation, which improves testing efficiency while maintaining reliable failure detection through proper signal control.
Data Source
AI summary
A test circuit capable of reducing the number of data I/O pins of a tester at a read operation includes a data masking control unit for masking a part of output data in response to an activation of one of an upper data masking signal to control a group of upper data pins and a lower data masking signal to control a group of lower data pins when a test mode signal is activated at a read operation.