Test Circuit Structures for Detecting Low Leakage Current Defects in Integrated Circuits
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Solution Overview
Problem
Conventional E-beam inspection techniques fail to detect low leakage current inducing defects such as dislocations and 'pipes' due to insufficient leakage current causing undetectable gray-level variations, particularly under dielectric layers in semiconductor devices.
Innovation Solution
The implementation of test circuits with enhanced design features like parallel semiconductor devices, localized substrate grounding, and close body contacts to increase sensitivity in detecting low leakage currents using electron beam-induced current (EBIC) or other high energy beam techniques, allowing for the identification of defects that conventional E-beam scans cannot detect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional E-beam inspection techniques are used, then inspection speed and ease of operation are maintained, but measurement precision and defect detection capability deteriorate due to insufficient sensitivity for low leakage current defects
Solution Approach 1:
The patent introduces an intermediary measurement mechanism (electron beam induced current measurement) that converts undetectable gray-level variations into measurable electrical signals. The test circuit structures act as intermediaries that amplify the electrical response to defects, enabling detection of low leakage current defects that would be invisible in conventional E-beam inspection images.
Solution Approach 2:
The patent replaces the optical detection mechanism (gray-level variation detection) with an electrical detection mechanism (current measurement). By substituting the detection principle from optical to electrical domain, the system gains sensitivity to low leakage current defects that produce insufficient optical contrast.
2Measurement precision
If test structures are added to enhance defect detection sensitivity, then measurement precision improves, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent segments the semiconductor device into functional application circuits and dedicated test circuits. The test circuits are separated and optimized specifically for defect detection functions, allowing enhanced sensitivity without compromising the simplicity and functionality of the main application circuits.
Solution Approach 2:
The test circuit structures are designed to serve multiple purposes: they function as both operational circuit elements and as sensitive detectors for defect characterization. This multi-functionality reduces the need for separate dedicated test structures, thereby limiting the increase in overall device complexity.
3Measurement precision
If conventional SRAM structures are used for dislocation inspection, then ease of manufacture is maintained, but measurement precision deteriorates as process improvements reduce SRAM cell sensitivity
Solution Approach 1:
The patent changes the design parameters of MOSFET structures in the test circuits, specifically creating high-sensitivity configurations with optimized dimensions and configurations that maintain high sensitivity to dislocations even as standard process improvements are implemented. This allows the test structures to adapt to evolving manufacturing processes while maintaining detection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the detection and localization of dislocations, pipes, and other defects by enhancing sensitivity to low leakage current levels, overcoming the limitations of conventional E-beam inspection methods and improving defect characterization in semiconductor devices.
Implementation Method 1
directing an electron current inducing beam to the test circuit, measuring a current between the first and the second contact pads in the test circuit, determining an electron beam induced current (EBIC)
Data Source
AI summary
A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.