Test Circuit Layout for Display Panel Signal Integrity
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Solution Overview
Problem
Conventional test circuit designs for OLED displays, particularly in the chip on film (COF) type, experience color mixing issues during the cell test process due to signal delays, leading to inefficiencies and resource wastage.
Innovation Solution
A test circuit layout structure for display panels is introduced, featuring a COF bonding region, power conductor regions, test circuit region, test pad regions, and electrostatic protection regions, with wires of specific resistivity bypassing power conductor regions in an insulation manner, utilizing multiple metal layers stacked and insulated to prevent signal delays and short-circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test circuit designs are used for COF type OLED displays, then the cell test process can be performed, but color mixing occurs due to signal delays
Solution Approach 1:
The patent changes the physical parameters of the wire conductors by using multiple metal layers with different resistivity characteristics. The first metal layer provides structural support while the second metal layer with lower resistivity minimizes signal delay, thereby maintaining signal integrity and preventing color mixing during cell testing
Solution Approach 2:
The patent employs a composite wire structure consisting of multiple metal layers (first metal layer and second metal layer) with different electrical properties. This composite approach combines the advantages of each metal layer to achieve both mechanical strength and optimal electrical conductivity, resolving the signal delay issue that causes color mixing
2Ease of manufacture
If wires with high resistivity are used to connect test regions, then manufacturing is easier, but signal delays occur causing color mixing
Solution Approach 1:
The patent optimizes the electrical parameters of the connection wires by implementing a multi-metal layer structure. The second metal layer is specifically selected with lower resistivity to reduce signal transmission time and prevent color mixing, while the overall structure remains manufacturable using standard thin-film deposition techniques
3Area of stationary object
If power conductor regions are placed close to test circuits for compact layout, then area is reduced, but short-circuits may occur
Solution Approach 1:
The patent resolves the spatial conflict between power conductor regions and test circuits by utilizing the vertical dimension with multiple insulated metal layers. This allows horizontal proximity for compact layout while maintaining vertical electrical isolation through insulation layers, preventing short-circuits
Solution Approach 2:
The patent introduces insulation layers as intermediary elements between the power conductor regions and test circuit wires. These insulation layers act as mediators that enable close proximity placement while preventing direct electrical contact, thus avoiding short-circuits in the compact border layout region
Data Source
AI summary
A test circuit layout structure for a display panel is disclosed and includes a chip on film (COF) bonding region having two ends connected to two power conductor regions extending toward an active area; a test circuit region located between the COF bonding region and the two power conductor regions; two test pad regions and two electrostatic protection regions are both distributed around two sides of the COF bonding region; wherein a plurality of wires extend from the test pad regions and are configured to couple the electrostatic protection regions, the COF bonding region, and the test circuit region; wherein resistivity of the wires and resistivity of the power conductor regions are the same; and wherein the wires bypass the power conductor regions disposed in the same layer as the wires, alternatively, the wires and the power conductor regions are overlapped in an insulation manner.