Test Circuit Gate Driver Driving Ability Evaluation
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Solution Overview
Problem
Existing display devices lack an effective test circuit to evaluate the driving ability of gate drivers, which is crucial for ensuring the proper functioning of display panels.
Innovation Solution
A test circuit is designed that includes a metal pattern and a test gate driver with multiple stages, where the test gate lines overlap the metal pattern and are connected in series with a first and second metal line, allowing for the implementation of a waveform substantially equivalent to a gate signal applied to a pixel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test circuit is added to evaluate gate driver driving ability, then the reliability of the display device is improved, but the device complexity increases
Solution Approach 1:
The test gate lines are designed to serve dual purposes: they function as both test structures for evaluating gate driver performance and as functional gate lines that can be integrated into the display panel. This multi-functionality allows the test circuit to provide reliable evaluation capability while minimizing the increase in overall device complexity by reusing existing structural elements.
2Measurement precision
If test gate lines with series-connected metal lines are used to reflect load, then the measurement precision of driving ability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs metal lines with different resistance characteristics (first metal line with lower resistance and second metal line with higher resistance) in a series configuration. By carefully selecting and adjusting the resistance parameters of these metal lines, the test gate lines can accurately reflect the load characteristics of the display area, enabling precise measurement of gate driver driving ability while maintaining manufacturability through standard fabrication processes.
Data Source
AI summary
A test circuit includes: a metal pattern disposed in a first area; a test gate driver disposed in a second area adjacent to the first area and including a plurality of test stages, each of which outputs a test gate signal; and a plurality of test gate lines overlapping the metal pattern in a plan view, connected to the plurality of test stages, respectively, each including a first metal line and a second metal line connected in series with the first metal line, and which receives the test gate signal.