Test Circuit Sharing Test Pad for Mode Transition and Current Measurement
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Solution Overview
Problem
The existing test circuits for semiconductor integrated circuits cannot share a test pad for transitioning to the test mode and current measurement, leading to increased chip area and manufacturing costs due to the need for multiple test pads.
Innovation Solution
A test circuit design that includes a p-channel MOS transistor, an n-channel MOS transistor, and a control circuit, allowing the test pad to be used for both mode transition and current measurement by controlling the n-channel MOS transistor to prevent extra current flow during the test mode, thereby reducing the number of test pads required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate test pad is provided for mode transition and current measurement, then the test circuit can reliably distinguish between test mode and measurement mode, but the number of test pads increases and chip area becomes large
Solution Approach 1:
The patent combines the mode transition function and current measurement function into a single test pad. The test pad serves dual purposes: accepting mode transition signals and measuring current during evaluation mode, thereby reducing the total number of test pads required and minimizing chip area occupation
Solution Approach 2:
The test pad is designed with multi-functionality to handle both mode transition signaling and current measurement tasks. By making the test pad universal, the patent eliminates the need for separate dedicated pads for each function, thus reducing chip area while maintaining operational reliability
2Area of stationary object
If the test pad is shared for mode transition and current measurement, then the chip area is reduced, but extra current flows through the test circuit during test mode
Solution Approach 1:
The patent applies preliminary action by using a control circuit to proactively manage the switching between modes. Before current measurement begins, the control circuit ensures the test circuit is properly configured and isolated from unwanted current paths, preventing extra current flow from occurring in the first place
Solution Approach 2:
The control circuit acts as an intermediary between the test pad and the test circuit elements. It mediates the connection and disconnection of current paths, ensuring that during test mode, current flows only through the intended measurement path and not through unintended routes that would cause extra current flow
3Object-generated harmful factors
If multiple test pads are used to avoid extra current flow, then the harmful current path is eliminated, but the manufacturing cost increases due to larger chip area
Solution Approach 1:
The patent merges the functionality of multiple test pads into a single shared test pad, reducing the total number of pads required. This consolidation decreases chip area occupation and associated manufacturing costs while the control circuit ensures proper current path management to eliminate harmful current flow
4Measurement precision
If the test circuit is designed with separate paths for mode transition and measurement, then current measurement accuracy is improved, but the device complexity increases
Solution Approach 1:
The test pad is designed as a universal interface that handles both mode transition and current measurement functions. This multi-functional design simplifies the overall device structure by eliminating the need for separate dedicated pads, while the control circuit manages the different operational modes to maintain measurement accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables the sharing of test pads, reducing the chip area and manufacturing costs by eliminating unnecessary current flow during the test mode, allowing for more compact semiconductor devices.
Implementation Method 1
a first p channel MOS transistor having a source connected to the test pad, and a gate to which a prescribed reference voltage is applied, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor
Data Source
AI summary
A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.