Test Circuit Interface Control Between Supply Stacks and Analog IPs
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Solution Overview
Problem
Existing test circuits for integrated circuits face issues such as yield loss due to analog intellectual property packages being operated outside rated voltages during test modes, excess power consumption, and repeated resets during voltage ramp-up, leading to delayed boot times and increased costs.
Innovation Solution
An electronic device with a power management circuit that generates output for voltage monitors to detect minimum thresholds and a control circuit to generate control signals for enabling or disabling interface with analog IPs, using separate voltage stacks for test mode entry and digital testing, reducing power consumption and avoiding improper operation of analog IPs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single voltage stack is used for test mode entry and during test modes, then device complexity is reduced, but analog intellectual property packages may be operated outside of their rated operating voltages resulting in failure to enter test mode and yield loss
Solution Approach 1:
The patent divides the voltage monitoring function into multiple voltage monitors (first voltage monitor for first supply voltage, second voltage monitor for second supply voltage) that operate independently during different test modes. This segmentation allows each monitor to be optimized for its specific voltage range, ensuring analog IPs operate within rated voltages while maintaining simple overall device architecture.
Solution Approach 2:
The patent implements dynamic voltage monitor masking controlled by a control circuit. The first voltage monitor is masked during digital test modes and unmasked during analog test modes, while the second voltage monitor operates oppositely. This dynamic switching allows a single voltage stack to safely support multiple test modes without operating analog IPs outside rated voltages.
2Device complexity
If the number of pins or pads used by the integrated circuit for testing is reduced, then device complexity and testing cost are reduced, but excess power consumption occurs and the life of the integrated circuit may be shortened
Solution Approach 1:
The patent implements preliminary voltage monitoring and control before actual testing begins. Voltage monitors continuously monitor supply voltages and the control circuit proactively masks or unmonitors based on predicted test mode requirements, preventing excess power consumption before it occurs and protecting the integrated circuit from stress during testing.
3Device complexity
If voltage monitoring is simplified to allow proper operation during test modes, then device complexity is reduced, but repeated reset occurs if any voltage drop occurs when supply voltage is ramping up during boot, causing delay in the start of applications
Solution Approach 1:
The patent implements dynamic masking of voltage monitors based on operational mode. During boot sequence, the control circuit unmonitors the first voltage monitor to allow rapid voltage ramp-up without triggering reset. During digital test modes, the first voltage monitor is masked to prevent false alarms from normal voltage variations. This dynamic approach simplifies monitoring while eliminating unnecessary reset delays.
Data Source
AI summary
An electronic device includes a power management circuit generating output for a plurality of voltage monitors that each detect whether voltages received from a test apparatus are at least a different minimum threshold. The power management circuit also generates a test enable signal indicative of whether the test apparatus is supplying the minimum required voltages to the electronic device. A control circuit receives the output for the plurality of voltage monitors and the test enable signal and generates at least one control signal as a function of the output for the plurality of voltage monitors and the test enable signal. An output circuit receives the at least one control signal and generates an interface control signal that selectively enables or disables interface with analog intellectual property packages within the electronic device, in response to the at least one control signal.