Test Circuit Synthesizing Signals With Inter-Block Delay
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Solution Overview
Problem
As the number of circuit blocks excluded from the test targets of a scan chain circuit increases, the load on the micro processing unit (MPU) grows significantly, requiring polling or interrupt handler processing to manage test instructions and results, which can be inefficient.
Innovation Solution
A test circuit that synthesizes first and second test result signals from different circuit blocks using an inter-block delay generation circuit and a synthesis circuit, producing a single synthesized test result signal with a delay, allowing identification of malfunctioning blocks without reading each individual result, thus reducing the MPU's load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of circuit blocks excluded from the test targets of the scan chain circuit is increased, then the testing capability is improved, but the load on the MPU greatly increases
Solution Approach 1:
The patent combines multiple test result signals from different circuit blocks into a single synthesized test result signal. The synthesis circuit integrates first and second test result signals, which have been delayed by different amounts, into one output signal that contains information about multiple circuit blocks, thereby reducing the number of signals the MPU must process.
Solution Approach 2:
The patent introduces a synthesis circuit as an intermediary between the test target circuits and the MPU. This synthesis circuit processes and combines multiple test result signals before they reach the MPU, acting as a mediator that reduces the processing burden on the MPU while preserving all necessary test information.
2Ease of operation
If polling or interrupt handler processing is executed to manage test instructions and results, then the test management is improved, but the processing time increases
Solution Approach 1:
The patent merges multiple test result signals into a single synthesized signal, which reduces the number of polling operations or interrupt handlers needed. Instead of managing multiple separate test result signals, the system only needs to manage one synthesized signal containing information about multiple circuit blocks.
Solution Approach 2:
The synthesis circuit performs preliminary processing of test result signals before they reach the MPU. By pre-combining and pre-processing the signals in the synthesis circuit, the system reduces the amount of work the MPU must do during polling or interrupt handling, thereby reducing processing time.
3Measurement precision
If each test result signal is read individually to identify failures, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The synthesis circuit serves as an intermediary that processes multiple test result signals and produces a synthesized signal containing information about multiple circuit blocks. This intermediary preserves the ability to identify failures in individual circuit blocks while simplifying the overall signal processing structure.
Solution Approach 2:
The patent uses different delay times for different test result signals as an additional dimension to encode information about which circuit block a test result comes from. By delaying signals by different amounts and then combining them, the system preserves block identification information in the temporal domain rather than requiring separate signal lines for each block.
Data Source
AI summary
A test circuit according to the present invention includes: a synthesis circuit that synthesizes a first test result signal output from a first test target circuit in response to a test instruction, and a second test result signal output from a second test target circuit in response to the test instruction; an inter-block delay generation circuit that delays the second test result signal with respect to the first test result signal; and a test result holding circuit that holds a synthesized test result signal every predetermined timing, the synthesized test result signal being output from the synthesis circuit.