Integrated Device Test Circuits for Stuck-At Fault Detection
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Solution Overview
Problem
Integrated circuits often contain faults, such as stuck-at faults, which are difficult to detect, especially for voltage level indicator pins at pads and analogue blocks, as existing methods lack explicit testing for these faults.
Innovation Solution
A test circuit and method that include an input node for a test signal, a transition circuit to generate voltage level indicators, and a data capture circuit to test for stuck-at faults, using a combination of power-on reset signals and logic gates to isolate and reset specific flops, enabling effective detection of stuck-at 1 faults without resetting the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing testing methods are used for voltage level indicator pins, then general circuit faults can be detected, but stuck-at faults in voltage level indicator pins at pads and analogue blocks cannot be effectively detected
Solution Approach 1:
The testing approach is segmented by creating separate testing paths for voltage level indicator pins at pads versus those at analogue blocks. The circuit divides the testing function into distinct segments: one segment handles pad voltage indicators through dedicated test circuits, while another segment handles analogue block voltage indicators through different test circuits, allowing each segment to be optimized for its specific detection requirements
Solution Approach 2:
Test circuits are introduced as intermediary elements between the voltage level indicator pins and the testing equipment. These intermediary test circuits include level indicators and capture circuits that mediate the detection process, enabling the external testing equipment to indirectly observe and capture the voltage levels at indicator pins without directly accessing them
2Reliability
If a test circuit is designed to test for stuck-at faults in voltage level indicator pins, then detection capability is improved, but device complexity increases due to additional test circuits and control logic
Solution Approach 1:
The test circuits for voltage level indicator pins are merged with the existing scan chain infrastructure and reset circuitry of the device. Test control logic is combined with the boundary scan register, and test signal distribution is integrated with the existing clock and reset networks, thereby reducing the need for completely separate testing components
Solution Approach 2:
The test circuits are designed with multi-functionality to handle multiple testing requirements. The same test circuit infrastructure is used for both pad voltage level indicators and analogue block voltage level indicators. The capture circuits can capture different signal types, and the reset logic serves both normal device reset and test circuit reset functions, reducing overall complexity through shared resources
3Productivity
If automated test equipment is used to capture voltage status, then testing efficiency is improved, but the requirement for explicit test control and signal routing increases complexity
Solution Approach 1:
The test control logic is designed to be dynamic rather than static, allowing the testing system to automatically configure signal routing based on the type of testing being performed. The control logic can dynamically enable or disable different test paths, switch between testing different voltage indicator pins, and adjust capture timing based on the specific test requirements, thereby managing complexity through adaptive control
Data Source
AI summary
Test circuits and methods for detecting faults in integrated devices are disclosed. In an embodiment, a circuit may include an input node configured to receive a test signal, and a transition circuit configured to generate a transit on at least one voltage level indicator pin dependent on the test signal. The circuit may also include a data capture circuit configured to capture the output of the at least one voltage level indicator pin to test for stuck-at faults. In another embodiment, a method may include receiving a test signal, generating a transit on at least one voltage level indicator pin dependent on the test signal, and capturing the output of the at least one voltage level indicator pin to test for stuck-at faults.