Test Clock Delay Circuit for BTI Pulse Width Compensation
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Solution Overview
Problem
Semiconductor devices face reliability degradation due to the Bias Temperature Instability (BTI) phenomenon, which affects the performance of MOS transistors, leading to increased threshold voltages and reduced drain currents, causing malfunctions in delay circuits.
Innovation Solution
A semiconductor device is designed with a test clock generation circuit, test data generation circuit, and control code generation circuit that utilize delay/selection signals and test clock signals to generate control codes, allowing for the compensation of BTI-induced degradation by controlling pulse widths and managing transistor degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOS transistors are used in delay circuits for normal operation, then device functionality is achieved, but reliability degrades due to BTI phenomenon over time
Solution Approach 1:
The patent applies preliminary action by performing BTI degradation compensation before it causes malfunction. The test clock generation circuit and test data generation circuit proactively measure delay changes caused by BTI, and the control code generation circuit pre-adjusts pulse widths to compensate for anticipated degradation, preventing malfunction before it occurs.
Solution Approach 2:
The patent implements feedback by using the delay/selection signal to continuously monitor the actual delay of the clock signal through the delay circuit. This measured delay information is fed back to the control code generation circuit, which adjusts the pulse width accordingly, creating a closed-loop system that compensates for BTI-induced threshold voltage shifts.
2Speed
If delay circuits are used to generate clock signals, then timing control is achieved, but pulse width increases due to BTI-induced threshold voltage increase
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the pulse width parameter in response to BTI-induced threshold voltage changes. The control code generation circuit modifies the pulse width parameter based on the delay/selection signal that reflects actual circuit delay, thereby compensating for BTI effects and maintaining consistent timing characteristics despite threshold voltage drift.
3Reliability
If test mode circuits are added to monitor and compensate BTI, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the test clock generation circuit and test data generation circuit to serve dual purposes: they function as normal clock and data generation circuits during regular operation, and simultaneously serve as test/measurement circuits for BTI monitoring when activated in test mode. This multi-functionality reduces the need for separate dedicated test circuits, thereby limiting the increase in device complexity.
Data Source
AI summary
A semiconductor device includes a test clock generation circuit, a test data generation circuit, and a control code generation circuit. The test clock generation circuit delays a clock signal based on a delay selection signal in a test mode to generate a test clock signal. The test data generation circuit delays data to generate test data. The control code generation circuit latches the test data based on the delay selection signal and the test clock signal to generate a control code.