External Test Clock Delay Compensation for High-Speed Debug
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Solution Overview
Problem
Current automotive test interfaces face challenges in achieving high data throughput due to timing constraints and delays in data communication between external test tools and vehicle computers, limiting the frequency of the test clock and thus the data transfer rate.
Innovation Solution
A testing tool with a programmable delay circuit that generates a delayed version of the test clock to compensate for transmission delays, allowing the data input circuitry to be clocked by this delayed clock, thereby ensuring timely data reception and increasing data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the test clock is increased to increase data throughput, then the data transfer rate is improved, but the timing constraint is violated due to unchanging transmission delays
Solution Approach 1:
The patent changes the timing parameter of the clock signal by introducing a programmable delay circuit that adjusts the phase of the test clock. This delay compensates for transmission delays in the data path, allowing higher clock frequencies to be used without violating timing constraints. The delay amount is programmable to match different data path lengths and transmission characteristics.
2Speed
If the test clock frequency is increased beyond a certain point, then higher data transfer rates are achieved, but data is received after the clock period ends causing malfunction
Solution Approach 1:
The patent applies preliminary action by advancing the clock signal to the data input circuitry before the data actually arrives. The programmable delay circuit calculates the expected transmission delay and compensates for it by adjusting the clock phase in advance, ensuring that the data input circuitry is ready to capture data at the correct moment even at high transfer rates.
3Productivity
If transmission delays are present in the data path, then timing constraints cannot be met at high clock frequencies, but increasing clock frequency is necessary for high throughput
Solution Approach 1:
The patent introduces an intermediary element - the programmable delay circuit - that mediates between the clock generation and data input circuitry. This intermediary compensates for the transmission delays by adjusting the clock phase, effectively canceling out the time loss introduced by the data path without requiring changes to the physical transmission medium.
Data Source
AI summary
A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.