Test Clock Signal Gating for At-Speed Semiconductor Scan Testing
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Solution Overview
Problem
Conventional test systems for semiconductor devices face challenges in generating high-frequency test clock signals due to the high cost of testers and limitations in pad frequency response, which restricts the ability to test internal logic circuits at their actual operating frequencies.
Innovation Solution
A method and apparatus for generating a test clock signal by receiving an external clock signal and a control signal, gating an internal clock signal to create a gated clock signal with a higher frequency, and selectively outputting either the external or gated clock signal based on the control signal, utilizing a clock signal multiplexer and logic circuits to manage the clock signals during shift and capture periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a tester with high clock frequency is used to test internal logic circuits at operating frequency over 400 MHz, then testing accuracy is improved, but tester cost increases significantly
Solution Approach 1:
The patent introduces an intermediary clock frequency conversion mechanism that translates the high-frequency internal clock signal (over 400 MHz) into a lower-frequency external test clock signal (under 200 MHz) that can be generated by conventional, less expensive testers. This mediator enables accurate high-frequency testing without requiring expensive high-frequency test equipment.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal through conversion. By transforming the high-frequency internal clock signal into a lower-frequency external test clock signal, the system allows conventional testers to accurately test high-frequency circuits by testing at a different (lower) frequency parameter.
2Speed
If pads with good frequency response are used to transmit high frequency signals, then signal transmission capability is improved, but production cost increases
Solution Approach 1:
The patent creates a copied version of the high-frequency clock signal at a lower frequency that can be transmitted through conventional pads. Instead of requiring pads to directly transmit high-frequency signals, the system generates a lower-frequency copy of the clock signal that achieves the same testing objective without demanding high-frequency pad performance.
3Ease of manufacture
If conventional testers with low clock frequency are used, then tester cost is reduced, but the ability to test high frequency internal logic circuits is worsened
Solution Approach 1:
The patent changes the frequency parameter of the test clock signal from high frequency (internal clock) to low frequency (external test clock). This parameter transformation allows conventional low-frequency testers to reliably test high-frequency circuits by testing at a converted lower frequency that preserves the essential timing and logical relationships.
Data Source
AI summary
A system and method of generating a test clock signal for scan testing of a main circuit in a semiconductor device includes receiving an external clock signal and a control signal and generating a gated clock signal by gating an internal clock signal based on the control signal. The internal clock signal has a frequency higher than a frequency of the external clock signal. One of the external clock signal and the gated clock signal is selectively output based on the control signal.