Programmable Test Clock Controllers for Parallel Domain Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional scan-based testing methods are inefficient in detecting delay-related faults in electronic circuits, particularly in devices with multiple clock domains, due to complex and costly test clock generation, inadequate synchronization of clock domains, and excessive data volume and time required for testing.
Innovation Solution
The implementation of programmable test clock controllers that configure different clock domains in parallel, allowing for concurrent execution of dynamic and static fault detection tests, reducing the need for frequent scan chain loading and unloading, and enabling simultaneous execution of intra-domain and inter-domain testing without reloading scan chains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay tests are used to detect dynamic faults, then fault detection capability is improved, but test data volume and test time increase significantly
Solution Approach 1:
The patent divides the circuit under test into multiple clock domains, each tested independently with dedicated test clock controllers. This segmentation allows parallel testing of different domains, reducing overall test time while maintaining comprehensive fault detection coverage for dynamic faults.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing multiple test clock controllers that operate simultaneously on different clock domains. This transforms the sequential testing approach into a parallel architecture, enabling multiple delay tests to execute concurrently without increasing data volume.
2Reliability
If delay tests are used to detect dynamic faults, then fault detection capability is improved, but test cost increases
Solution Approach 1:
The test clock controllers are designed as reconfigurable, multi-functional units that can be programmed to implement different test protocols (broadside, last-shift-launch, stuck-at tests) across multiple clock domains. This universality eliminates the need for separate dedicated test equipment for each protocol, reducing overall test system cost while maintaining comprehensive fault detection.
3Measurement precision
If multiple clock domains are tested sequentially, then test accuracy is maintained, but test time increases
Solution Approach 1:
The patent segments the testing process by assigning dedicated test clock controllers to specific clock domains, allowing each domain to be tested independently and simultaneously. This maintains the precision required for each individual domain's timing constraints while dramatically increasing overall test throughput through parallel execution.
4Reliability
If scan chains are reloaded frequently for different test protocols, then test coverage is improved, but test time increases
Solution Approach 1:
The patent implements preliminary configuration of test clock controllers with all necessary test protocols and parameters before actual testing begins. Scan chains are loaded once with comprehensive test patterns that cover multiple protocols, and the reconfigurable controllers switch between protocols without requiring scan chain reloads, eliminating repetitive loading time while maintaining full test coverage.
Data Source
AI summary
Methods and computer readable media for performing scan-based testing of circuits using one or more test clock control structures are disclosed. In one embodiment, a method includes performing an intra-domain test to exercise a first subset of domains of the plurality of circuits implementing dynamic fault detection test patterns. It also includes performing an inter-domain test to exercise a second subset of domains of the plurality of circuits implementing dynamic fault detection test patterns. The dynamic fault detection test patterns can include, for example, last-shift-launch test patterns and broadside test patterns. In various embodiments, the method can include configuring different programmable test clock controllers to test different domains substantially in parallel.