Test Device for Asynchronous Circuit Synthesis on FPGA
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Solution Overview
Problem
It is challenging to test fully customized circuits, especially those with asynchronous elements, on Field Programmable Gate Arrays (FPGAs) due to difficulties in evaluating and synthesizing such circuits effectively.
Innovation Solution
A test device is developed that models test-object circuits with a one-to-one or one-to-multi relationship, generating various types of model circuits based on delay amounts, allowing for efficient synthesis and testing by selecting appropriate model circuits, such as shifting or counting circuits, to minimize time and space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fully customized circuits with asynchronous elements are tested on FPGA, then testing capability is improved, but synthesis difficulty and evaluation complexity increase
Solution Approach 1:
The patent introduces an intermediary processing system that converts asynchronous circuit descriptions into synchronous circuit models before FPGA synthesis. This intermediary step acts as a mediator between the asynchronous test-object circuit and the synchronous FPGA synthesis process, enabling successful synthesis of circuits that would otherwise be incompatible with standard FPGA tools.
Solution Approach 2:
The patent creates a synchronous circuit model as a copy or representation of the original asynchronous circuit. This model circuit replicates the functional behavior of the asynchronous circuit but uses synchronous design principles, making it synthesizable on FPGA while preserving the essential testing capabilities.
2Measurement precision
If model circuits are generated with one-to-multi relationship based on delay amount, then testing accuracy is improved, but circuit area increases
Solution Approach 1:
The patent segments the modeling approach by creating different types of model circuits (first-typed and second-typed) based on delay amount thresholds. This segmentation allows the system to select appropriate model complexity levels for different delay requirements, optimizing the balance between testing accuracy and circuit area.
Solution Approach 2:
The patent changes the delay parameter to determine model circuit type selection. By establishing threshold values for delay amounts, the system dynamically adjusts the model circuit configuration to match the actual delay characteristics of the test-object circuit, improving accuracy while controlling area growth.
3Reliability
If first-typed model circuit is used with circuit area proportional to delay amount, then delay coverage is improved, but resource consumption increases
Solution Approach 1:
The patent implements a dynamic model selection mechanism that adapts the model circuit type based on the actual delay amount of the test-object circuit. When delay exceeds a threshold, the system switches from first-typed to second-typed model circuits, dynamically adjusting resource allocation to match actual testing needs.
Solution Approach 2:
The patent applies partial action by using the simpler first-typed model circuit for small delay amounts where full complexity is unnecessary, and only employs the more resource-intensive second-typed model circuit when delay requirements exceed the threshold, avoiding excessive resource consumption.
4Productivity
If second-typed model circuit is used with constant circuit area, then resource efficiency is improved, but delay precision may be reduced
Solution Approach 1:
The patent uses parameter changes (delay amount threshold) to determine when to switch between model circuit types. This parameter-based decision mechanism ensures that delay precision is maintained by selecting the appropriate model type based on the actual delay characteristics of the circuit being tested.
Data Source
AI summary
A test device includes a circuit modelling portion suitable for generating one or more model circuits by modelling a test-object circuit with a one-to-one or a one-to-multi relationship between the test-object circuit and the model circuits, and a test operation portion suitable for synthesizing the model circuits and performing a test operation on the model circuits.