Test Device Reference Voltage Adjustment for High-Frequency Signal Delay

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Solution Overview

Problem

Conventional self-test methods for devices under test cannot effectively evaluate the entire device, including output and input buffers near the terminal side, especially when dealing with high-frequency logic signals, due to signal delay issues.

Innovation Solution

A testing apparatus comprising a comparator and driver that adjust reference voltages to compensate for signal delays, and equalizers that set amplification amounts for frequency components to ensure proper signal transmission and reception, allowing for comprehensive testing of devices under test, including output and input buffers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a testing apparatus makes a loop-back of a signal output from the device under test to the device under test, then it is possible to test the whole of the device under test including the output buffer and the input buffer, but it is impossible to perform a testing using a logic signal of relatively high frequency because a signal is delayed between the device under test and the testing apparatus

Engineering Contradiction:
Improvetesting coverageVSAvoidsignal frequency
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent applies preliminary action by measuring the signal delay between the device under test and the testing apparatus in advance, then using this measured delay value to adjust the reference voltage of the comparator and the reference logic level of the driver beforehand. This pre-adjustment ensures that high-frequency logic signals can be properly tested without experiencing timing issues during the actual test execution.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If the reference voltage of the comparator is fixed, then the comparator operation is simple, but it cannot compensate for signal delay variations

Engineering Contradiction:
Improvecomparator configurationVSAvoiddelay compensation
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies dynamics by making the reference voltage of the comparator adjustable rather than fixed. The comparator setting unit dynamically adjusts the reference voltage based on the measured signal delay value, allowing the system to adapt to different delay conditions while maintaining proper comparator operation. This dynamic adjustment enables delay compensation without significantly increasing system complexity.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables effective testing of devices under test with high-frequency logic signals by compensating for delays, ensuring proper signal loop-back and evaluation of the entire device, including output and input buffers, without deteriorating the transmission path characteristics.

Implementation Method 1

a comparator for receiving a signal output from the device under test and converting the signal into a logic signal by comparing the signal with a first reference voltage

Methodology Applied
Scientific EffectVoltage comparison:

Implementation Method 2

a driver for amplifying a logic signal to be output to the device under test on the basis of a second reference voltage

Methodology Applied
Scientific EffectSignal amplification:

Implementation Method 3

an equalizer able to set an amplification amount for each frequency component... a reception side equalizer for receiving and amplifying a signal output from the device under test

Methodology Applied
Scientific EffectFrequency-selective amplification:

Data Source

PatentUS7453932B2Test device and setting method
Publication Date: 2008.11.18 ADVANTEST CORP
  • US7453932B2 patent drawing
  • US7453932B2 patent drawing
  • US7453932B2 patent drawing

AI summary

A testing apparatus for testing a device under test is provided, wherein the testing apparatus includes: a comparator for receiving a signal output from the device under test and converting the signal into a logic signal by comparing the signal with a first reference voltage; a driver for amplifying a logic signal to be output to the device under test on the basis of a second reference voltage and outputting to the device under test; a comparator setting unit for determining the first reference voltage so as to compensate for a delay amount of a reception signal received from the device under test and setting the comparator to be the first reference voltage; and a driver setting unit for determining the second reference voltage on the basis of the reference voltage of the comparator and setting the driver to be the second reference voltage.