Test Electrode Pad Layout for Semiconductor Wafer Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing configurations for laying out test elements on semiconductor wafers face challenges in efficiently managing increasing numbers of superimposition marks, thickness monitoring marks, and test elements, leading to increased chip size and layout area, while also complicating reliable contact between test probes and electrode pads.
Innovation Solution
Test electrode pads are disposed in alignment in one row, with test elements formed below them and electrically coupled to adjacent pads, allowing for high-density placement without increasing the layout area, and probe pins are brought into contact with alternate pads to ensure reliable testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test elements and superimposition marks are disposed in scribe areas, then reliability evaluation can be performed, but the layout area increases and chip size grows
Solution Approach 1:
The patent merges the functions of test elements and superimposition marks by disposing them in the same scribe area. Test elements are arranged in a matrix pattern where certain positions serve both as test transistors and as locations for superimposition detection marks, thereby combining testing and alignment functions in a single integrated structure that reduces overall layout area.
Solution Approach 2:
The patent utilizes the vertical dimension by disposing test elements in a matrix arrangement with multiple layers. Superimposition detection marks are placed in overlapping positions with test elements in the same scribe area, effectively using spatial overlap in the planar dimension to reduce the required layout area while maintaining both testing and alignment capabilities.
2Productivity
If the number of test elements is increased for high integration, then evaluation capability improves, but the pitch between test elements becomes small and probe contact reliability deteriorates
Solution Approach 1:
The patent segments the scribe area into multiple functional zones within the matrix arrangement. Test elements are disposed in specific rows and columns with sufficient spacing, while superimposition marks are placed in alternate positions. This segmentation allows maintaining adequate pitch between test elements for reliable probe contact while still increasing overall evaluation capability through the matrix structure.
3Length of moving object
If test electrode pads are disposed in zigzag form, then pitch between pads is reduced, but layout complexity increases
Solution Approach 1:
The patent employs an asymmetric matrix arrangement for test elements in the scribe area. Rather than symmetric patterns, test transistors are disposed in specific row-column combinations that optimize pitch reduction while maintaining manufacturing simplicity. The asymmetric layout allows reduced pitch between adjacent test elements while avoiding the complexity of zigzag patterns.
Data Source
AI summary
The present invention aims to increase the number of test elements of a TEG without increasing the area of each of slice areas. Test electrode pads are disposed in alignment in one row in each of areas separated from semiconductor chips provided over a semiconductor wafer. Test elements are formed corresponding to these test electrode pads and in areas lying directly therebelow. Electrode terminals of the test elements are electrically coupled to the test electrode pads adjacent to the corresponding electrode pads and the test electrode pads further adjacent thereto with being spaced one test electrode pad apart. Upon testing, probe pins are brought into contact with the odd-numbered test electrode pads to conduct testing. Next, the probe pins are brought into contact with the even-numbered test electrode pads while being shifted by one electrode pad pitch thereby to conduct testing.