Test Element Group Integration in Semiconductor Scribe Regions
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Solution Overview
Problem
Current semiconductor wafer processing methods lack efficient integration of test element groups (TEGs) in scribe regions, which hinders accurate measurement of electric properties in circuit regions, leading to potential defects and reduced reliability.
Innovation Solution
The integration of test element groups (TEGs) in scribe regions using a double patterning lithography method, forming high-density repeating patterns and enlarged active regions to accommodate test circuits, allowing for precise measurement of electric properties through test transistors and pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test element groups are integrated in scribe regions using conventional single patterning lithography, then the manufacturing process is simple, but the measurement precision of electric properties is insufficient and defects are not detected accurately
Solution Approach 1:
The patent divides the patterning process into two separate steps: first forming mandrels with a first pitch, then forming test element groups with a second pitch that is a multiple of the first pitch. This segmentation allows independent optimization of each patterning step, achieving high-density test structures without requiring a single complex ultra-high-resolution lithography step.
Solution Approach 2:
The patent creates a hierarchical structure where test element groups are formed within scribe regions that already contain circuit regions. The test structures are nested in the spaces between circuit regions, utilizing existing process infrastructure and wafer handling procedures. Multiple test elements are arranged in matrix patterns within each scribe region, creating a compact nested arrangement that maximizes measurement coverage.
2Measurement precision
If more test elements are added to scribe regions to improve measurement coverage, then the measurement precision improves, but the device complexity and processing difficulty increase
Solution Approach 1:
The patent designs test element groups that can measure multiple electric properties simultaneously using a unified test structure. Each test element group includes test transistors, source/drain regions, and contact pads that can be configured to measure different properties (threshold voltage, transconductance, mobility) by varying the measurement conditions, eliminating the need for separate dedicated test structures for each property.
Solution Approach 2:
The patent varies the pitch parameter between the first mandrel formation and second test element formation steps, using a second pitch that is a multiple of the first pitch. This parameter change allows the same lithography equipment to achieve different density requirements for different structural layers, simplifying the overall process while enabling high-density test element placement.
3Manufacturing precision
If conventional lithography is used without double patterning, then the manufacturing process is simpler, but the manufacturing precision of high-density test patterns cannot be achieved
Solution Approach 1:
The patent performs preliminary mandrel formation with a first pitch that is easier to achieve with conventional lithography. These mandrels serve as templates for subsequent spacer formation and test element patterning. By preparing the mandrel structure first, the process enables precise high-density test patterns to be formed through secondary lithography steps that build upon the preliminary structure rather than requiring a single difficult high-precision step.
Data Source
AI summary
According to one or more embodiments of the disclosure, an apparatus comprising a plurality of active regions on a semiconductor substrate, an active bridge region connecting two active regions among the plurality of active regions, and a plurality of test circuit elements on the active bridge region and the two active regions.