Integrated Test Element Unit for Display Panel Process Monitoring
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Solution Overview
Problem
Existing display manufacturing technologies face challenges in real-time detection of process abnormalities, leading to increased production costs and time wastage due to the need for multiple test element units and complex processes, especially in top gate structure devices using low-temperature polysilicon technology.
Innovation Solution
A real-time test element unit or test element group that monitors and adjusts process parameters in multi-layer processes, allowing for real-time detection of abnormalities and reducing production costs by combining tests for overlapping characteristics, process capability, and capacitances using a single unit with inter-layered capacitors and test lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test element units are designed in different layers for single-function testing, then detection coverage is improved, but device complexity and production cost increase
Solution Approach 1:
The patent combines multiple test functions into a single integrated test element unit. The test element includes test lines extending in different directions (first direction and second direction perpendicular to the first) that can simultaneously perform overlapping characteristic tests, process capability tests, and capacitance tests. This merging approach eliminates the need for separate test element units for each function, thereby reducing device complexity while maintaining comprehensive detection coverage.
Solution Approach 2:
The test element unit is designed with multi-functional capabilities. The same test element can perform multiple types of tests including overlapping characteristic tests (by measuring offset between test lines in different directions), process capability tests (by measuring widths of test lines with different widths), and capacitance tests (through inter-layer capacitors formed between test lines in different layers). This universal test element replaces multiple specialized test elements, reducing overall device complexity.
2Manufacturing precision
If multiple photo masks and complicated processes are used for top gate structure devices, then manufacturing precision is improved, but production time and cost increase
Solution Approach 1:
The patent incorporates test elements into the display device structure during the manufacturing process itself, rather than adding them separately afterward. The test lines are formed simultaneously with the actual device lines using the same photo masks and processing steps. This preliminary integration allows process capability to be tested during manufacturing without requiring additional time-consuming separate testing steps.
Solution Approach 2:
The test elements serve dual purposes: they function as both test structures for process monitoring and as part of the overall device architecture. The test lines are formed using the same material layers and processing steps as the functional elements, meaning the manufacturing process creates both the device and its own test infrastructure in one go. This self-service approach eliminates the need for separate dedicated test structures that would require additional manufacturing steps.
3Device complexity
If single-layer single-function testing is performed, then device complexity is reduced, but real-time detection capability is lost
Solution Approach 1:
The patent transitions from single-layer testing to multi-layer testing within a single integrated test element unit. Test lines are formed in different layers (first layer and second layer) with inter-layer capacitors connecting them. This dimensional transition to three-dimensional multi-layer structure allows the test element to perform multiple functions simultaneously while maintaining overall structural integration, thereby enabling real-time detection without significantly increasing device complexity.
4Manufacturing precision
If comprehensive tests are performed on all process parameters, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent merges multiple test functions into a single integrated test element that can perform overlapping characteristic tests, process capability tests, and capacitance tests simultaneously. By combining these tests in one unified structure rather than performing them separately, the system achieves comprehensive process parameter control without the time penalty of sequential testing, as all test functions are embedded in the same manufacturing flow.
Data Source
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AI summary
The present disclosureprovides a test element unit, an array substrate, a display panel, a display apparatus and a method of manufacturing an array substrate. The test element unit includes: a plurality of layers of test patterns, each layer of test pattern including at least one test block and at least one capacitor being formed between test blocks located in different layers, and, two electrodes of each of capacitors being two test blocks located in different layers,respectively, so that it can determined whether or not corresponding components and devices formed in the display region meet requirements by detecting the test patterns formed in the test region.