Digital Test Equipment Pattern Memory Reduction
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Solution Overview
Problem
Digital test systems require excessive memory storage due to the need for separate enable vectors for each test vector and response vector, leading to inefficiencies in bandwidth and cost, especially as electronic systems and integrated circuits become more complex.
Innovation Solution
A test system configuration that uses a first memory for test vectors, a second memory for selection codes, and a third memory for configuration sets, where selection codes associate test vectors with unique configuration sets, reducing the number of configuration sets and enabling efficient communication with a device under test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate enable vectors are stored for each test vector and response vector, then the test system can properly control driver and compare circuits, but the memory storage requirements increase significantly
Solution Approach 1:
The patent combines separate drive enable vectors and compare enable vectors into a single integrated enable vector. This merging reduces memory storage requirements by eliminating redundant storage of enable information that was previously duplicated across multiple vectors, while still providing the necessary control signals for both driver and compare circuits during test operations.
Solution Approach 2:
The patent creates a universal enable vector structure that serves multiple functions: it controls both driver circuits and compare circuits, and can be applied to both test vectors and response vectors. This multi-functional approach eliminates the need for separate enable vectors for different purposes, thereby reducing overall memory requirements while maintaining full control capability.
2Adaptability or versatility
If the pattern memory stores both data bits and enable bits for each vector, then the system can control which channels are enabled for driving and comparing, but the bandwidth and cost efficiency decrease
Solution Approach 1:
The patent merges drive enable and compare enable control into a single enable vector, reducing the total number of bits that must be stored and transmitted. This consolidation improves bandwidth efficiency by reducing the data width required for memory operations and enhances cost efficiency by reducing the overall memory capacity needed while preserving full channel enable control capability.
3Reliability
If twice the memory and bus width are allocated for unidirectional signal nodes, then the system can properly handle both drive and compare operations, but the system becomes less cost effective
Solution Approach 1:
The patent combines drive and compare enable control into a single integrated enable vector, which reduces the required bus width and memory capacity by approximately half for unidirectional signal nodes. This merging maintains full operational capability for both drive and compare functions while significantly improving cost effectiveness by reducing hardware resources required.
Solution Approach 2:
The universal enable vector structure provides multi-functional control that handles both drive and compare operations within a single vector framework. This approach eliminates the need for separate enable vectors and associated memory and bus resources, thereby reducing manufacturing costs while maintaining reliable operation for both drive and compare functions.
Data Source
AI summary
A test system and method of configuring therefor. A test system includes a plurality of interface circuits for communicating with a device under test (DUT). The test system further includes a first memory for storing test vectors, a second memory for storing selection codes, and a third memory for storing configuration sets. Each selection code indicates an association between a test vector and a configuration set. Each configuration set may be associated with one or more of the test vectors. The configuration sets include information for configuring the interface circuits during communications between the test system and the DUT for each test vector. Each configuration set in the third memory is unique with respect to the other configuration sets, and the number of configuration sets may be less than the number of test vectors.