Automated Test Equipment Traffic Capture Circuit for Failure Debug

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Solution Overview

Problem

Conventional mass testing systems lack the capability to capture detailed communication information leading up to a testing failure, limiting the understanding of failure causes and requiring expensive protocol analyzers that are not feasible for large-scale deployment.

Innovation Solution

Implementing automated test equipment with traffic capture circuits, capture memory, and routing logic to capture and analyze communications in real-time, allowing for the determination of failure types and generation of human-readable reports.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If a highly capable protocol analyzer is placed between every device under test and its corresponding device tester, then detailed failure information can be obtained, but the cost becomes prohibitive and physical deployment becomes infeasible

Engineering Contradiction:
Improvefailure informationVSAvoidnumber of protocol analyzers
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent combines the protocol analyzer functionality with the existing device tester by integrating a traffic capture circuit and capture memory into the tester architecture. This merging allows the tester to perform both testing and failure analysis functions, eliminating the need for separate expensive protocol analyzers at each test point.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The device tester is enhanced to perform multiple functions: it not only conducts the primary testing operations but also captures communications traffic, stores it in capture memory, and analyzes it to determine failure types. This multi-functionality reduces the need for additional specialized equipment.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Loss of information

If external protocol analyzer testers are used to capture communications, then detailed protocol analysis is possible, but communications between test system controller and functional blocks remain invisible

Engineering Contradiction:
Improvecommunications informationVSAvoidvisibility of internal communications
Core Design Contradiction:
Loss of informationVSAdaptability or versatility

Solution Approach 1:

The traffic capture circuit is nested within the downstream port of the FPGA-based tester, allowing it to capture communications at multiple levels: both the external communications between tester and device under test, and the internal communications between the tester's functional blocks and controller. This nested structure provides comprehensive visibility.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Device complexity

If conventional testing systems are used without protocol analyzers, then cost and complexity are reduced, but little is known regarding the nature of device failures

Engineering Contradiction:
Improvetesting system configurationVSAvoidfailure nature information
Core Design Contradiction:
Device complexityVSLoss of information

Solution Approach 1:

The traffic capture circuit continuously captures and stores communications traffic in capture memory before a failure occurs. This preliminary action ensures that complete communication records are available for analysis even after the failure happens, enabling thorough investigation of the failure nature without requiring complex real-time analysis during the failure event.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10379158B2Real-time capture of traffic upon failure for protocol debug
Publication Date: 2019.08.13 ADVANTEST CORP
  • US10379158B2 patent drawing
  • US10379158B2 patent drawing
  • US10379158B2 patent drawing

AI summary

An automated test equipment for simultaneous testing of multiple devices includes a traffic capture circuit configured to capture communications with a device under test, a capture memory configured to store the communications captured by the traffic capture circuit, and a routing logic configured to read the communications from the capture memory, e.g., random access memory (RAM). There may be one of each of the traffic capture circuit, the capture RAM, and the routing logic for each device of the multiple devices.